Abstract: Systems, methods, and apparatuses for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array are described.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

Abstract: Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.

Abstract: In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.

Abstract: In some embodiments an apparatus may comprise a data circuit, a clock circuit to synchronize the data circuit; and a sampling circuit to sample a clock signal from a separate clock domain, the sampling circuit may control the clock circuit in response to the sampled clock signal and to delay the data circuit from providing data if it would result in data corruption due to clock misalignment.

Abstract: Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.

Abstract: An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a first modified IC design layout.