Abstract: A method for object detection of an object based on measurement data from at least one point-based sensor capturing the object. The measurement data, which are based on a point cloud having a plurality of points and associated features, are processed in that, in a point-based first processing step having at least one processing level, the input-side features of the point cloud are realized as learned features, and are enriched at least by information about relationships between the points, and in a grid-based second processing step having at least one processing level, the learned features are then transferred onto a model grid having a plurality of grid cells, and cell-related output data are then generated. An image detection device, a computer program, and a storage unit, are also described.

Abstract: A sensor system with a first semiconductor die part and with a second semiconductor die part is proposed, wherein the first semiconductor die part has a microelectromechanical sensor element, wherein the second semiconductor die part covers the microelectromechanical sensor element, wherein the second semiconductor die part has a via for electrically contacting the microelectromechanical sensor element, in particular directly. A method for producing a sensor system is also proposed.

Abstract: A sensor system with a first semiconductor die part and with a second semiconductor die part is proposed, wherein the first semiconductor die part has a microelectromechanical sensor element, wherein the second semiconductor die part covers the microelectromechanical sensor element, wherein the second semiconductor die part has a via for electrically contacting the microelectromechanical sensor element, in particular directly. A method for producing a sensor system is also proposed.

Abstract: A method for estimating noise in a radar sensor, which generates a digital spectrum which indicates a received signal strength as a function of at least one discrete locating parameter, and on this spectrum a CFAR detection is carried out to decide whether an examined cell in the locating space contains a genuine radar target or just noise and a determination of a noise level is also carried out on the basis of the signal strengths in a selection of neighboring cells in the vicinity of the examined cell. The CFAR detection precedes the determination of the noise level and cells identified in the CFAR detection as target cells are excluded from the selection of the neighboring cells.

Abstract: A sensor system with a first semiconductor die part and with a second semiconductor die part is proposed, wherein the first semiconductor die part has a microelectromechanical sensor element, wherein the second semiconductor die part covers the microelectromechanical sensor element, wherein the second semiconductor die part has a via for electrically contacting the microelectromechanical sensor element, in particular directly. A method for producing a sensor system is also proposed.

Abstract: In a method of fabricating a semiconductor structure, a carbon containing mask is fabricated over a dielectric layer. The mask exposes the surface of the dielectric layer at least partly in a region between two adjacent conducting lines. A contact hole is etched into the dielectric layer in the region between the two adjacent conducting lines.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; depositing a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region; forming a mask layer on said first protective layer in said memory cell region; exposing said cap of said at least one gate stack in said peripheral device region by removing said first protective layer in said peripheral device region in an etch step wherein said mask layer acts as a mask in said memory cell region; removing said mask layer and said first protective layer from said memory cell region; for

Abstract: Embodiments of the invention relate to a method of fabricating an integrated circuit, including etching of a layer that includes a high k material in the form of a metal oxide composition, wherein an etchant is used that includes a silicon halogen composition.

Abstract: In a method of fabricating a semiconductor structure, a carbon containing mask is fabricated over a dielectric layer. The mask exposes the surface of the dielectric layer at least partly in a region between two adjacent conducting lines. A contact hole is etched into the dielectric layer in the region between the two adjacent conducting lines.

Abstract: An integrated circuit having an active semiconductor device is formed comprising a trench defined by conductor lines previously formed.

Abstract: In one aspect, the invention provides a fabrication method. Before the fabrication of the structure, a mask layer, for example a hard mask, is applied to a layer. The mask layer has at least two layers composed of materials that can be etched selectively with respect to one another. In a first etching process, the structure is introduced into the layer. Subsequently, the first etching process is interrupted at a point in time in order to etch away a topmost layer of the hard mask selectively with respect to the underlying layer by means of a second etching process and, subsequently, the first etching process is continued for fabricating the structure with the new topmost layer.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; depositing a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region; forming a mask layer on said first protective layer in said memory cell region; exposing said cap of said at least one gate stack in said peripheral device region by removing said first protective layer in said peripheral device region in an etch step wherein said mask layer acts as a mask in said said memory cell region; removing said said mask layer and said first protective layer from said memory cell r

Abstract: A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.

Abstract: A memory device includes an array of memory cells and a storage capacitor for storing information. Each memory cell includes an access transistor. The access transistor includes first and second source/drain regions, a channel disposed between the first and the second source/drain regions, and a gate electrode electrically insulated from the channel and adapted to control the conductivity of the channel. The access transistor is at least partially formed in the semiconductor substrate. The storage capacitor is adapted to be accessed by the access transistor. The storage capacitor includes at least first and second storage electrodes and at least a capacitor dielectric disposed between the first and the second storage electrodes. Each of the first and the second storage electrodes is disposed above the substrate surface.

Abstract: A memory device includes an array of memory cells and a storage capacitor for storing information. Each memory cell includes an access transistor. The access transistor includes first and second source/drain regions, a channel disposed between the first and the second source/drain regions, and a gate electrode electrically insulated from the channel and adapted to control the conductivity of the channel. The access transistor is at least partially formed in the semiconductor substrate. The storage capacitor is adapted to be accessed by the access transistor. The storage capacitor includes at least first and second storage electrodes and at least a capacitor dielectric disposed between the first and the second storage electrodes. Each of the first and the second storage electrodes is disposed above the substrate surface.

Abstract: A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.

Abstract: A solenoid valve having a magnet assembly and an injector body connected thereto, the magnet assembly and the injector body being joined together using a crimped retaining ring as the connecting element.

Abstract: A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon.

Abstract: A method for etching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon.