Patents by Inventor Daniel KOMAROMY

Daniel KOMAROMY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9262627
    Abstract: Methods, devices, and systems for detecting return-oriented programming (ROP) exploits are disclosed. A system includes a processor, a main memory, and a cache memory. A cache monitor develops an instruction loading profile by monitoring accesses to cached instructions found in the cache memory and misses to instructions not currently in the cache memory. A remedial action unit terminates execution of one or more of the valid code sequences if the instruction loading profile is indicative of execution of an ROP exploit involving one or more valid code sequences. The instruction loading profile may be a hit/miss ratio derived from monitoring cache hits relative to cache misses. The ROP exploits may include code snippets that each include an executable instruction and a return instruction from valid code sequences.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: February 16, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Daniel Komaromy, Alexander Gantman, Brian Rosenberg, Arun Balakrishnan, Renwei Ge, Gregory Rose, Anand Palanigounder
  • Publication number: 20140372701
    Abstract: Methods, devices, and systems for detecting return-oriented programming (ROP) exploits are disclosed. A system includes a processor, a main memory, and a cache memory. A cache monitor develops an instruction loading profile by monitoring accesses to cached instructions found in the cache memory and misses to instructions not currently in the cache memory. A remedial action unit terminates execution of one or more of the valid code sequences if the instruction loading profile is indicative of execution of an ROP exploit involving one or more valid code sequences. The instruction loading profile may be a hit/miss ratio derived from monitoring cache hits relative to cache misses. The ROP exploits may include code snippets that each include an executable instruction and a return instruction from valid code sequences.
    Type: Application
    Filed: August 29, 2014
    Publication date: December 18, 2014
    Inventors: Daniel KOMAROMY, Alexander Gantman, Brian Rosenberg, Arun Balakrishnan, Renwei Ge, Gregory Rose, Anand Palanigounder
  • Patent number: 8839429
    Abstract: Methods, devices, and systems for detecting return-oriented programming (ROP) exploits are disclosed. A system includes a processor, a main memory, and a cache memory. A cache monitor develops an instruction loading profile by monitoring accesses to cached instructions found in the cache memory and misses to instructions not currently in the cache memory. A remedial action unit terminates execution of one or more of the valid code sequences if the instruction loading profile is indicative of execution of an ROP exploit involving one or more valid code sequences. The instruction loading profile may be a hit/miss ratio derived from monitoring cache hits relative to cache misses. The ROP exploits may include code snippets that each include an executable instruction and a return instruction from valid code sequences.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: September 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Daniel Komaromy, Alex Gantman, Brian M. Rosenberg, Arun Balakrishnan, Renwei Ge, Gregory G. Rose, Anand Palanigounder
  • Patent number: 8776223
    Abstract: A method, apparatus, and/or system for execution prevention is provided. A state indicator for a first subset of a plurality of memory pages of executable code in a memory device is set to a non-executable state. A state indicator for a second subset of the plurality of memory pages is set to an executable state, where the second subset of the plurality of memory pages includes indirection stubs to functions in the first subset of the plurality of memory pages. Upon execution of an application, a function call is directed to a corresponding indirection stub in the second subset of the plurality of memory pages which modifies the state indicator for a corresponding function in the first subset of the plurality of memory pages prior to directing execution of the called function from the first subset of the plurality of memory pages.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: July 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Arun Balakrishnan, Alexander Gantman, Renwei Ge, Daniel Komaromy, Yinian Mao, Anand Palanigounder, Brian M. Rosenberg
  • Publication number: 20130185792
    Abstract: A method, apparatus, and/or system for execution prevention is provided. A state indicator for a first subset of a plurality of memory pages of executable code in a memory device is set to a non-executable state. A state indicator for a second subset of the plurality of memory pages is set to an executable state, where the second subset of the plurality of memory pages includes indirection stubs to functions in the first subset of the plurality of memory pages. Upon execution of an application, a function call is directed to a corresponding indirection stub in the second subset of the plurality of memory pages which modifies the state indicator for a corresponding function in the first subset of the plurality of memory pages prior to directing execution of the called function from the first subset of the plurality of memory pages.
    Type: Application
    Filed: January 16, 2012
    Publication date: July 18, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Arun Balakrishnan, Alexander Gantman, Renwei Ge, Daniel Komaromy, Yinian Mao, Anand Palanigounder, Brian M. Rosenberg
  • Publication number: 20130117843
    Abstract: Methods, devices, and systems for detecting return-oriented programming (ROP) exploits are disclosed. A system includes a processor, a main memory, and a cache memory. A cache monitor develops an instruction loading profile by monitoring accesses to cached instructions found in the cache memory and misses to instructions not currently in the cache memory. A remedial action unit terminates execution of one or more of the valid code sequences if the instruction loading profile is indicative of execution of an ROP exploit involving one or more valid code sequences. The instruction loading profile may be a hit/miss ratio derived from monitoring cache hits relative to cache misses. The ROP exploits may include code snippets that each include an executable instruction and a return instruction from valid code sequences.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 9, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Daniel KOMAROMY, Alex Gantman, Brian M. Rosenberg, Arun Balakrishan, Renwei Ge, Gregory G. Rose, Anand Palanigounder