Patents by Inventor Daniel Kueck
Daniel Kueck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9923066Abstract: A semiconductor device includes a source zone electrically connected to a first load terminal, a contiguous zone isolating the source zone from a drift zone, and a trench extending into a semiconductor body along a vertical direction and including a first electrode electrically connected to a control terminal and an insulator in contact with the contiguous zone and which isolates the first electrode from the semiconductor body. The insulator has, at a trench bottom region, a first thickness along the vertical direction, and, at a trench top region, a second thickness along a lateral direction, the first thickness being greater than the second thickness by a factor of at least 1.5. The contiguous zone is arranged in contact with the insulator and extends further along the vertical direction than the trench, and the trench bottom region and the contiguous zone overlap along the lateral direction.Type: GrantFiled: July 27, 2016Date of Patent: March 20, 2018Assignee: Infineon Technologies AGInventors: Daniel Kueck, Thomas Aichinger, Franz Hirler, Anton Mauder
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Publication number: 20170345905Abstract: A semiconductor device includes trench gate structures extending from a first surface into a semiconductor body from a wide-bandgap semiconductor material. The trench gate structures separate mesa portions of the semiconductor body from each other. In the mesa portions, body regions form first pn junctions with a drain structure and directly adjoin first mesa sidewalls. Source regions in the mesa portions form second pn junctions with the body regions, wherein the body regions separate the source regions from the drain structure. The source regions directly adjoin the first mesa sidewalls and second mesa sidewalls opposite to the first mesa sidewalls.Type: ApplicationFiled: May 24, 2016Publication date: November 30, 2017Inventors: Ralf Siemieniec, Dethard Peters, Romain Esteve, Wolfgang Bergner, Thomas Aichinger, Daniel Kueck, Roland Rupp, Bernd Zippelius, Karlheinz Feldrapp, Christian Strenger
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Publication number: 20170117352Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.Type: ApplicationFiled: January 6, 2017Publication date: April 27, 2017Inventors: Romain Esteve, Dethard Peters, Wolfgang Bergner, Ralf Siemieniec, Thomas Aichinger, Daniel Kueck
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Publication number: 20170103894Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.Type: ApplicationFiled: October 7, 2016Publication date: April 13, 2017Inventors: Thomas Aichinger, Wolfgang Bergner, Romain Esteve, Daniel Kueck, Dethard Peters, Victorina Poenariu, Gerald Reinwald, Roland Rupp, Gerald Unegg
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Patent number: 9577073Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.Type: GrantFiled: December 11, 2014Date of Patent: February 21, 2017Assignee: Infineon Technologies AGInventors: Romain Esteve, Dethard Peters, Wolfgang Bergner, Ralf Siemieniec, Thomas Aichinger, Daniel Kueck
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Publication number: 20170040425Abstract: A semiconductor device includes a source zone electrically connected to a first load terminal, a contiguous zone isolating the source zone from a drift zone, and a trench extending into a semiconductor body along a vertical direction and including a first electrode electrically connected to a control terminal and an insulator in contact with the contiguous zone and which isolates the first electrode from the semiconductor body. The insulator has, at a trench bottom region, a first thickness along the vertical direction, and, at a trench top region, a second thickness along a lateral direction, the first thickness being greater than the second thickness by a factor of at least 1.5. The contiguous zone is arranged in contact with the insulator and extends further along the vertical direction than the trench, and the trench bottom region and the contiguous zone overlap along the lateral direction.Type: ApplicationFiled: July 27, 2016Publication date: February 9, 2017Applicant: Infineon Technologies AGInventors: Daniel KUECK, Thomas AICHINGER, Franz HIRLER, Anton MAUDER
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Publication number: 20170032964Abstract: A Method for protecting a surface of a substrate includes processing the substrate, forming a pyrolytic carbon layer on at least one surface of the substrate, and subjecting the substrate to thermal treatment, specifically above a temperature of about 1300° C., typically above about 1400° C.Type: ApplicationFiled: July 20, 2016Publication date: February 2, 2017Inventors: Daniel Kueck, Guenter Denifl, Werner Eigler, Roland Moennich
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Patent number: 9543414Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.Type: GrantFiled: December 11, 2014Date of Patent: January 10, 2017Assignee: Infineon Technologies AGInventors: Romain Esteve, Dethard Peters, Wolfgang Bergner, Ralf Siemieniec, Thomas Aichinger, Daniel Kueck
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Publication number: 20160172468Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.Type: ApplicationFiled: December 11, 2014Publication date: June 16, 2016Inventors: Romain Esteve, Dethard Peters, Wolfgang Bergner, Ralf Siemieniec, Thomas Aichinger, Daniel Kueck
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Publication number: 20150171078Abstract: A semiconductor device incudes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.Type: ApplicationFiled: February 23, 2015Publication date: June 18, 2015Inventors: Daniel Kueck, Rudolf Elpelt
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Patent number: 9029974Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.Type: GrantFiled: September 11, 2013Date of Patent: May 12, 2015Assignee: Infineon Technologies AGInventors: Romain Esteve, Jens Konrath, Daniel Kueck, David Laforet, Cedric Ouvrard, Roland Rupp, Andreas Voerckel, Wolfgang Werner
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Patent number: 8994078Abstract: A semiconductor device includes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.Type: GrantFiled: June 29, 2012Date of Patent: March 31, 2015Assignee: Infineon Technologies Austria AGInventors: Daniel Kueck, Rudolf Elpelt
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Publication number: 20150069411Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Inventors: Romain Esteve, Jens Konrath, Daniel Kueck, David Laforet, Cedric Ouvrard, Roland Rupp, Andreas Voerckel, Wolfgang Werner
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Publication number: 20140001558Abstract: A semiconductor device includes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Daniel Kueck, Rudolf Elpelt