Abstract: A bandgap reference voltage circuit is provided that substantially prevents noise sensitivity. The bandgap reference voltage circuit includes an operational amplifier, transistors, and a resistive element on one input of the operational amplifier. The resistive element substantially prevents noise from creating a non-zero mean change in current across one of the transistors. Thus, the resistive element substantially precludes noise from being rectified by a transistor, so that the output reference voltage of the bandgap reference voltage circuit is substantially stable and fixed.

Abstract: A circuit for implementing a first order noise shaping apparatus for use in data converters employing thermometer-code based elements is disclosed. Raw thermometer code is rotated by up to four columns of shifters such that the code is rotated up to 15 positions. In this manner, the elements of the data converter may equally participate in the conversion process, thereby minimizing the effects of mismatched elements in a data converter by distributing errors due to mismatched elements. Such a process may be used in digital to analog converters and analog to digital converters such that a suitable data weighted algorithm can be used.

Abstract: Analog signals representing individual digital values (+3, +1, -1, -3) of data pass through a telephone line to a receiver. These signals may first be provided in a pseudo random sequence. A linear echo canceller and a first adder at the receiver simultaneously eliminate, to some extent, echo signals resulting from second analog signals transmitted through the telephone line by the receiver. A non-linear echo canceller and a second adder further significantly reduce the echo signals and specifically reduce non-linear components in the echo signals. Adjustable signal delays achieve optimal performance of the linear and non-linear echo cancellers. In one inventive embodiment, each echo canceller includes a memory which stores, for each terminal in such echo canceller, data representing (a) the pseudo random sequence and (b) coefficients for adjusting the signals in such sequence. Such data for each terminal in such echo canceller is recorded in the memory for introduction to the next terminal in the memory.

Abstract: A data processing system which has an interface circuit that interfaces the data processing system to input devices. The interface includes an input means such as a pad for conducting signal levels from the interface devices to the data processing system. A digitizer, such as a Schmitt trigger, digitizes the signal levels to signal levels that are acceptable by the data processing system. An output line conditioner conditions the data lines that are connected to the digitizers to prevent overdriving of the data lines by the digitizers. Line drivers are used for driving the digitized system on the data lines throughout the data processing system.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. A multiplier circuit produces a single state multiply function separate from the ALU. One input to the ALU passes through a full-width shifter with sign extension. The on-chip program memory is a RAM which may be configured as either program or data memory space. The processor may operate will all off-chip program memory and a large on-chip data memory, or with program execution from on-chip RAM (downloaded from the off-chip program memory) using a block move instruction.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program fitch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program memory may be a RAM and this additional RAM may be configured as either program or data memory space.

Abstract: A digital multiplication circuit for a microprocessor utilizes a modified Booth algorithm for implementing the digital multiplication of two numbers and includes a Booth recoder for recoding the multiplier into a selected number, n, of Booth operation sets where n is a positive integer that equals one-half the number of bits in the multiplier. Each operation set is applied to a second plurality of n partial products selectors which are connected in cascade arrangement according to multiplicand sets and wherein each partial product selector multiplicand set implements one of the recoded Booth operation sets. The outputs of the partial product selectors are summed by a summation means and a domino circuit means provides an evaluation pulse for each member of the partial product selector at the completion of the Booth operation set that is connected to the partial product selector.