Patents by Inventor Daniel L. Lowrance
Daniel L. Lowrance has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11853207Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.Type: GrantFiled: June 2, 2021Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Patent number: 11854634Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.Type: GrantFiled: August 31, 2020Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L Lowrance, Peter Feeley
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Patent number: 11836078Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.Type: GrantFiled: January 14, 2022Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L Lowrance, Peter Feeley
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Patent number: 11817164Abstract: The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.Type: GrantFiled: February 25, 2022Date of Patent: November 14, 2023Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Patent number: 11783185Abstract: Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.Type: GrantFiled: March 28, 2022Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Joshua Phelps, Peter B. Harrington
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Publication number: 20220215261Abstract: Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.Type: ApplicationFiled: March 28, 2022Publication date: July 7, 2022Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Joshua Phelps, Peter B. Harrington
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Publication number: 20220180954Abstract: The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.Type: ApplicationFiled: February 25, 2022Publication date: June 9, 2022Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Publication number: 20220138100Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Patent number: 11295209Abstract: Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.Type: GrantFiled: December 20, 2019Date of Patent: April 5, 2022Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Joshua Phelps, Peter B. Harrington
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Patent number: 11264112Abstract: Apparatuses and methods related to a memory system including a controller and an array of memory cells are provided. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.Type: GrantFiled: December 4, 2020Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Patent number: 11226896Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.Type: GrantFiled: August 31, 2020Date of Patent: January 18, 2022Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Publication number: 20210286722Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.Type: ApplicationFiled: June 2, 2021Publication date: September 16, 2021Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Publication number: 20210192333Abstract: Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Joshua Phelps, Peter B. Harrington
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Patent number: 11036631Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.Type: GrantFiled: November 3, 2017Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Publication number: 20210090674Abstract: The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.Type: ApplicationFiled: December 4, 2020Publication date: March 25, 2021Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Publication number: 20200394135Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Publication number: 20200395091Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Patent number: 10861573Abstract: Apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.Type: GrantFiled: October 3, 2019Date of Patent: December 8, 2020Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Patent number: 10777292Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.Type: GrantFiled: September 30, 2019Date of Patent: September 15, 2020Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Patent number: 10761980Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.Type: GrantFiled: June 17, 2019Date of Patent: September 1, 2020Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley