Abstract: A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.

Abstract: A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of component cores onto a die at predetermined locations with a reusable mask set; providing a custom blocking mask that includes opaque regions that positionally correspond with the component cores on the die; superimposing the custom blocking mask with a generic array type cell mask to form superimposed masks; and using the superimposed masks to print generic array type cells onto the die with the exception of the predetermined locations where the set of component cores reside.

Abstract: A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.

Abstract: An integrated circuit (IC) including at least one combinational logic path. The features in the combinational logic path are self compensating for out-of-focus effects. In particular, field effect transistor (FET) gates may be iso-focally spaced such that the gate (critical dimension) may move with changing focus, but the gate length remains the same. Alternately, logic circuits in a path may self-compensate for focus effects on individual circuits.

Abstract: A method and system for layout optimization relative to lithographic process windows which facilitates lithographic constraints to be non-localized in order to impart a capability of printing a given circuit with a process window beyond the process windows which are attainable with conventional simplified design rules. Pursuant to the method and system, lithographic capability and process windows are maximized to satisfy local circuit requirements and in order to achieve a maximally efficient layout.

Abstract: An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

Abstract: In connection with the manufacture of chips having partitioned logic, a partitioned mask layout approach. This approach provides the chip exposure pattern as a set of partitions corresponding to macros or core functions and also handles glue logic and interconnect. A result of this approach is a simplified, cost-effective process that does not defer customization to other, potentially more time-consuming and inefficient tasks.

Abstract: Structure for enhancing data processing applications by the ability to write both horizontal and vertical lines into a two-dimensional array. The disclosure describes a mapping for storing an array in 64K memory chips, and the required data transformations, address calculations, and chip hardware. As described, the mapping and hardware provide bit addressability in both horizontal and vertical directions.

Abstract: This specification describes a decoder for a programmable logic array (PLA) having opposite ends of input lines of the array connected to outputs of different decoders. Previously two-bit decoders were arranged on opposite sides of the array to generate input variables from two sets of two different input signals each and feed those input variables to four input lines. Here, instead of using two-bit decoders, four one-bit decoders are positioned on each side. The outputs of these one-bit decoders are programmable to change the connections between them and the input lines of the array. The arrangement permits the decoders to perform one-bit, two-bit decoding on signals on the same side of the input lines, to do two-bit decoding on signals on opposite sides of the array and in combination with other sets of decoders to do three and four-bit decoding of input signals.

Abstract: This specification describes a decoder for use in a programmable logic array (PLA) of the type having opposite ends of input lines of the array connected to outputs of different decoders. Instead of using the outputs of two two-bit decoders to drive four input lines, as was previously done, four one-bit decoders are used to drive the four input lines. This arrangement permits the one-bit decoders with minor modifications to be used to perform four one-bit decodes of four input signals, two two-bit decodes on two sets of two input signals on either side of the array and one two-bit decode on two input signals that are on opposite sides of the array.

Abstract: This specification describes arrays for performing logic functions which include circuitry for testing the arrays to see if the arrays will perform the logic functions that they were designed to perform. This circuitry eliminates the need for storing information as to logic functions performed by any particular array and allows a uniform testing sequence to be used in testing all the arrays.