Abstract: A needle implantable atrial fibrillation monitor includes a plurality of terminals that generate a terminal voltage when the needle implantable atrial fibrillation monitor is implanted in a patient's body. An analog processing circuit generates a monitoring signal based on the terminal voltage. An analog to digital converter converts the monitoring signal to monitoring data. A processor analyzes the monitoring data, generates events and compresses the event data and that generates compressed data in response thereto. A memory stores the compressed data. An RF interface transmits the compressed data to a base station via RF signaling when the needle implantable atrial fibrillation monitor is implanted in the patient's body.

Abstract: The analog adaptive equalizer provides convergence of an error signal by decoupling the error canceller, the automatic gain control and the filter to provide truly adaptive error minimization. The invention includes an automatic gain control (AGC) circuit for providing broadband amplification of an input signal to generate an AGC output signal, a filter for receiving the AGC output signal and providing high frequency signal conditioning to generate a filter output signal, an error detection circuit for generating an error signal representing the difference between the filter output signal and an expected output signal and a calculator for receiving the error signal and providing a gain correction signal to the automatic gain circuit to adjust the gain of the automatic gain circuit and a filter control signal to adjust the filter range of the filter, the gain correction signal and the filter control signal being used to cancel the error signal.

Abstract: A timing recovery apparatus for recovering the timing from sparse timing information in multi-level or partial response codes. The timing recovery apparatus includes a switch for sampling an incoming line code signal according to a selectable sample rate, a feed forward equalizer for filtering the sampled signal, a decision feedback equalizer for cancelling intersymbol interference in the filtered signal and for recovering the timing in the sampled signal. The timing recovery circuit creates a phase correction signal in response to a signal received from the feed forward equalizer and thereby control the sample rate of the sample switch so that the signal-to-noise ratio at the node before the decision is maximized. The voltage controlled crystal oscillator may be controlled within a certain frequency range by using a second phase detector which compares the phase of the signal controlling the sampling of the incoming line code with a reference clock.

Abstract: A data communication system employing predetermined equalized waveforms for transmit equalization is disclosed. Serial NRZ data is received from a network controller and utilized to select from memory its equivalent as predistorted and filtered Manchester encoded data. Predetermined waveforms in memory are representative of the analog waveform produced when predistorted digital Manchester encoded data is passed through a high order transmit filter. Data from memory drives a digital to analog converter (DAC) to reconstruct the waveforms into analog form. A line driver having an integrated single pole low pass filter impresses the equalized waveform on to the transmission line.

Abstract: A high frequency receive equalizer for baseband data recovery is disclosed utilizing a frequency selective equalization filter to restore dispersed pulses into a recoverable form. The frequency selective equalization filter has a plurality of independently adjustable stages. Received pulses are passed through an equalization filter whose output is monitored by equalizer feedback control means. The feedback control means adjusts the amount of equalization applied until the amplitude of the equalized pulses reaches a predetermined level.

Abstract: A two terminal line driver employing predistortion is disclosed, for driving data over a lossy transmission line such as a twisted pair cable at speeds on upwards of 10 Mbit/s. The driver is designed for voltage output operation wherein fullstep and halfstep information is actively encoded into a voltage level provided for at the output terminals. The driver provides a fullstep voltage spanning the supply rails and a halfstep voltage having a selectable controlled amplitude of a predetermined value. Fat bits resulting from the biphase encoding format are predistorted by dropping the amplitude to a predetermined value, equalizing the relative power content.

Abstract: A device (16) for reducing the intrinsic low frequency jitter within a Digital Phase lock loop (17). A Digital Phase lock loop high speed clock signal (4) is produced by a multistage oscillator (5), producing a plurality of identical frequency signals, each differing in phase. An adjust signal (18) generated by the Digital Phase lock loop output clock signal (3) causes an adjacent phase angle to be selected as the high speed clock signal (4), thereby reducing the period of the clock signal (4) and, in effect, accelerating the high speed clock signal (4). The current state of the selected phase and the appropriate selection of adjacent phase is monitored by a ten stage shift register (20-29), the presence of a "high bit" within a particular shift register block causing selection of the individual phase (6-15) which serves as the input to that particular shift register stage. An error correction circuit (40) detects the presence of more or less than a single high bit within the shift register stages (20- 29).

Abstract: A current-controlled oscillator includes a plurality of switches for generating a time delay signal, each switch including an MOS transistor operatively coupled to the next gate by means including a capacitor, the final MOS transistor being connected to the initial MOS transistor by a feedback conductor also operatively connected with a capacitor. The frequency of the oscillator is varied by varying current injected into the oscillator.

Abstract: A phase locked loop circuit includes a phase detector and an oscillator associated therewith, and a voltage-to-current converter for providing that lag signals sent thereto from the phase detector provide increased signal to the oscillator, and lead signals sent thereto from the phase detector provide decreased signal to the oscillator.