Abstract: An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.

Abstract: The invention provides novel inhibitors of hedgehog signaling that are useful as a therapeutic agents for treating malignancies where the compounds have the general formula I: wherein A, X, Y R1, R2, R3, R4, m and n are as described herein.

Abstract: The disclosure provides systems and methods for data analysis of experimental data. The analysis can include reference data that are not directly generated from the present experiment, which reference data may be values of the experimental parameters that were either provided by a user, computed by the system with input from a user, or computed by the system without using any input from a user. Another example of such reference data may be information about the instrument, such as the calibration method of the instrument.

Abstract: Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.

Abstract: A system that includes a plurality of encapsulation blocks having a plurality of digital signal processing (DSP) blocks provided with preconfigured logic functions and a plurality of pacing control networks operatively connected with the plurality of DSP blocks. The system also includes a streaming cross bar operatively connected with each encapsulation block of the plurality of encapsulation blocks. Each encapsulation block of the plurality of encapsulation blocks includes a DSP block of the plurality of DSP blocks and a pacing control network of the plurality of the pacing control networks. Each DSP block of the plurality of DSP blocks is independently and separately connected with the streaming cross bar via the plurality of pacing control networks.

Abstract: An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.

Abstract: A logic power network provided in an application-specific integrated circuit (ASIC). The ASIC includes a central processor. The ASIC also includes at least one intellectual property (IP) core operatively connected with the central processor and having a set of electrical components provided therein. The ASIC also includes a network-on-chip (NOC) operatively connected with the central processor and the at least one IP core. The ASIC also includes a logic power network operatively connected with the central processor, the at least one IP core and the set of electrical components therein, and the NOC. The logic power network is adapted to control power of the at least one IP core and the set of electrical components provided in the at least one IP Core individually and separately.

Abstract: A port protection network provided with a joint test action group (JTAG) core and method of use. The port protection network includes an agent device operatively connected with a streaming bus and a test access port (TAP) of the JTAG core. The port protection network also includes a master device operatively connected with the streaming bus and the TAP of the JTAG core. In the port protection network, the agent device is configured to selectively restrict access to the master device through the JTAG core.

Abstract: An on-chip firewall circuit for providing secure on-chip communication is disclosed. The firewall circuit includes a configurable table of port IDs along with a configurable setting for each port ID to either provide the corresponding port ID with open access to the components of a secure enclave (SE) module or restricted access. If access is restricted, then the command is rerouted to a portion of the secure memory within the SE module, where it can be read only via a secure processing device within the SE module. The secure processing device may require additional verification of the port ID before executing the command stored within the secure memory. In this way, unsecure devices from outside of the SE module can be configured to have no direct access to any of the components within the SE module.

Abstract: A method of detecting abnormal or malicious activity in a point-to-point or packet-switched data communication network includes tapping a link in the network to obtain a data stream transmitted from a node of the network in parallel with transmission of the data stream through the network. The tap is non-invasive because it does not interfere with the normal traversal of the data stream across the network. This is useful for certain applications, such as mission-critical systems, where it is desirable to monitor the network and inspect the data without adversely impacting or otherwise interfering with the normal operation of the system. The method further includes decoding a communication protocol encoded in the data stream to obtain payload data from the data stream, analyzing the payload data to detect abnormal or malicious activity, and notifying a host of the network of the detected abnormal or malicious activity in the payload data.

Abstract: A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.

Abstract: A power distribution device includes an input, an output, a power switch controller, and a voltage isolation device. The power distribution device includes, and is designed to provide power to, for example, non-radiation-tolerant or non-radiation hardened components for use in low Earth orbit (LEO) missions. The input is configured to receive power from a power source. The output is configured to provide the power to an electrical load. The power switch controller is configured to selectively operate the power distribution device in a first mode responsive to a first event, and to selectively operate the power distribution device in a second mode responsive to a second event. The voltage isolation device includes a plurality of switches configured, in the first mode, to pass the power between the input and the output, and, in the second mode, to interrupt the passage of the power between the input and the output.

Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.

Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.

Abstract: A computer device includes an interface board, a plurality of peripheral component interface (PCI) busses on the interface board, and a plurality of device card connectors carried by the interface board. The plurality of device card connectors include at least one first device card connector coupled to first and second PCI busses synchronous with one another, and at least one second device card connector coupled to the second PCI bus and to a third PCI bus asynchronous with the second PCI bus. The PCI busses are thus connected so that the PCI busses may be added in groups according to the number of device card connectors supported by the interface board, and not by the loading constraints of the PCI busses themselves. By defining both synchronous and asynchronous device card connectors, device cards requiring either synchronous or asynchronous communications may be utilized by the computer device.

Abstract: A communications adapter receives and transmits simultaneously packet and/or isochronous data between two interfaces; a network and a host bus system. The adapter stores the isochronous and packet data in receive and transmit queues configured in a FDDI RAM buffer. A controller manages the transfers of the data into and out of the queues. A local bus interacts with the system to provide descriptors of addresses in the system for transfers of data out of the queues to the system or the network. The controller is programmable to provide a variable threshold for the transfer of data between the queues and the system or the network. A systems interface unit handles the transfer of data to/from the system and allows data to bypass the queues and directly access the system or the network.

Abstract: A communications adapter receives and transmits simultaneously packet and/or isochronous data between two interfaces; a network and a host bus system. The adapter stores the isochronous and packet data in receive and transmit queues configured in a FDDI RAM buffer. A controller manages the transfers of the data into and out of the queues. A local bus interacts with the system to provide descriptors of addresses in the system for transfers of data out of the queues to the system or the network. The controller is programmable to provide a variable threshold for the transfer of data between the queues and the system or the network. A systems interface unit handles the transfer of data to/from the system and allows data to bypass the queues and directly access the system or the network.

Abstract: A communications adapter receives and transmits simultaneously packet and/or isochronous data between two interfaces; a network and a host bus system. The adapter stores the isochronous and packet data in receive and transmit queues configured in a FDDI RAM buffer. A controller manages the transfers of the data into and out of the queues. A local bus interacts with the system to provide descriptors of addresses in the system for transfers of data out of the queues to the system or the network. The controller is programmable to provide a variable threshold for the transfer of data between the queues and the system or the network. A systems interface unit handles the transfer of data to/from the system and allows data to bypass the queues and directly access the system or the network.

Abstract: A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.

Abstract: A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.