Abstract: An integrated circuit package with a buffer providing radiation protection to memory elements and components is described. The integrated circuit packages and the incorporated buffers provide a protective distance between potential sources of internal radiation particles within the integrated circuit package and any memory elements/components which may be sensitive to radiation such as alpha particles. This protective distance allows for the integrated circuit packages to be completed or assembled without needing added more expensive or redundant memory components.

Abstract: An integrated circuit package with a buffer providing radiation protection to memory elements and components is described. The integrated circuit packages and the incorporated buffers provide a protective distance between potential sources of internal radiation particles within the integrated circuit package and any memory elements/components which may be sensitive to radiation such as alpha particles. This protective distance allows for the integrated circuit packages to be completed or assembled without needing added more expensive or redundant memory components.

Abstract: An approach to creating a semiconductor chip including a semiconductor substrate with one or more topside metal layers and one or more backside metal layers. The approach creates the semiconductor chip with one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate and one or more inductors in the one or more backside metal layer. Furthermore, the approach creates the semiconductor chip with one or more through silicon vias extending through the semiconductor substrate connecting the one or more inductors in the one or more backside metal layers and the one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate.

Abstract: An approach to creating a semiconductor chip including a semiconductor substrate with one or more topside metal layers and one or more backside metal layers. The approach creates the semiconductor chip with one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate and one or more inductors in the one or more backside metal layer. Furthermore, the approach creates the semiconductor chip with one or more through silicon vias extending through the semiconductor substrate connecting the one or more inductors in the one or more backside metal layers and the one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate.

Abstract: Systems and methods are provided for modeling the power consumption of intellectual property (IP) components of a chip by defining how individual pins operate in a particular application. A method is provided for performing a power analysis of an IP design. The method includes generating an activity map that reflects power attributes for each pin that impacts power in the IP design. The method also includes generating specific activity assertions based on the power attributes and chip level usage information for the IP design. The method further includes using a computing device to perform the power analysis using the specific activity assertions.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.

Abstract: A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.

Abstract: A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value.

Abstract: A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet.

Abstract: A computer implemented power optimization method that generates statistics relating to the clock gating of a set of components in a VLSI design. A set of components, including those components which are not clock gated, are identified. The generation of statistics related to clock gating testing identify whether one or more components of the set of components may be clock gated.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A high speed signal transmission system employs differential receivers for receiving data signals transmitted over circuit transmission lines. One input each receiver is coupled to the output of a transmission line and to a termination network. The termination network generates a termination voltage and a source impedance that is matched to the characteristic impedance of the transmission line. The other input of the receiver is coupled to a reference voltage. The termination voltage may be adjusted by programming signals while keeping the source impedance constant and matched to the transmission line. A test mode may be employed where known data signals are transmitted and received and the termination voltage is adjusted while monitoring the states of the received signals on the output of the receivers. In this manner, the system may be optimized or tested for noise margin in an actual operation environment without resorting to probing methods.

Abstract: A high speed signal transmission system employs differential receivers for receiving data signals transmitted over circuit transmission lines. One input each receiver is coupled to the output of a transmission line and to a termination network. The termination network generates a termination voltage and a source impedance that is matched to the characteristic impedance of the transmission line. The other input of the receiver is coupled to a reference voltage. The termination voltage may be adjusted by programming signals while keeping the source impedance constant and matched to the transmission line. A test mode may be employed where known data signals are transmitted and received and the termination voltage is adjusted while monitoring the states of the received signals on the output of the receivers. In this manner, the system may be optimized or tested for noise margin in an actual operation environment without resorting to probing methods.

Abstract: Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.