Abstract: Disclosed is an interocular fluid shunting assembly including a contact or interface plate and one or more fluid drainage tubes. According to embodiments there may be provided two tubes draining fluid to different locations. According to embodiments, a biodegradable polymer may be used to hinder fluid flow through at least one tube at initial insertion.

Abstract: A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs) arranged into a plurality of CU groups. The memory is arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups. For each CU group a respective first memory address is determined and for each CU group, the data in the associated memory macro-block is accessed at the respective first memory address.

Abstract: A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.

Abstract: A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs) arranged into a plurality of CU groups. The memory is arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups. For each CU group a respective first memory address is determined and for each CU group, the data in the associated memory macro-block is accessed at the respective first memory address.

Abstract: A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.

Abstract: The invention proposes a simple method for controlling distributed functional units (FU) in a system. It offloads the main system processor from intermediate status monitoring. The sequencer controlled system comprises a plurality of functional units, a processor operatively coupled to the plurality of functional units through a bus, a sequencer having a set of registers, and an interrupt source register configured for interrupt polling. The registers are configured to control the timing of at least one operation of the functional units with stored instructions for each of the functional units. The processor sets up at least some of the registers through the bus for the initial configuration and the sequencer is activated by the processor.

Abstract: The invention proposes a simple method for controlling distributed functional units (FU) in a system. It offloads the main system processor from intermediate status monitoring. The sequencer controlled system comprises a plurality of functional units, a processor operatively coupled to the plurality of functional units through a bus, a sequencer having a set of registers, and an interrupt source register configured for interrupt polling. The registers are configured to control the timing of at least one operation of the functional units with stored instructions for each of the functional units. The processor sets up at least some of the registers through the bus for the initial configuration and the sequencer is activated by the processor.

Abstract: The present invention is concerned with a system for the filtration of molten material. The system is particularly useful for removing MgO impurities present in molten magnesium chloride electrolyte. The invention also comprises a method for removing solid particles from molten materials. Preferred molten materials include magnesium, aluminum, magnesium chloride electrolyte and aluminum electrolyte. The concentration of solid remaining in the molten material is less than 0.05 wt %.