Abstract: A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded mode and flattening the plurality of register file cells with a single thread when the processor is operating in a single threaded mode. The register file cells correspond to threads of the multithreaded processor.

Abstract: A microprocessor includes multiple register files. In a single thread mode, the microprocessor allows a single thread to have access to multiple ones of the register files. In a multi-thread mode, each thread has access to respective ones of the register files. In the multi-thread mode, multiple threads are simultaneously executing. Circuitry and hardware are provided to facilitate the respective modes and to facilitate transitions between the modes.

Abstract: In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K-2, the number of instructions issued for cycle K-1 and the number of instructions speculatively issued in cycle K-1 that have produced a cache hit, and subtracting from the sum the number of instructions enqueued for cycle K-1. The result indicates the number of invalid instructions in the queue cycle K. The number of invalid entries instructions, the number of issued instructions, and the number of enqueued instructions are preferably represented as flat vectors, so that adding is performed by shifting in one direction, while subtracting is performed by shifting in the opposite direction. The result is compared with either the number of instructions to be enqueued in the present cycle, which number is encoded, or with a predetermined value.

Abstract: A microprocessor includes multiple register files. In a single thread mode, the microprocessor allows a single thread to have access to multiple ones of the register files. In a multi-thread mode, each thread has access to respective ones of the register files. In the multi-thread mode, multiple threads are simultaneously executing. Circuitry and hardware are provided to facilitate the respective modes and to facilitate transitions between the modes.

Abstract: A system and method for scheduling instructions that are executed in the microprocessor are provided. The microprocessor executes multiple instructions per cycle that may have dependencies on execution results of other instructions. A scoreboard is utilized to schedule instructions. The scoreboard indicates dependencies between instructions. The scoreboard also controls the indication of dependencies based on the issuance of old instructions. The scoreboard includes a register for each instruction. The register has elements each of which corresponds to one of other instructions. An element of the register for an instruction is set where the element corresponds to one of other instructions which the instruction depends on.

Abstract: A spill/fill engine detects when a register window spill trap or a register window fill trap is imminent. The spill/fill engine takes steps to avoid the trap so as to not incur an undue amount of overhead in servicing the trap with a software trap handler. The spill/fill engine may be implemented in hardware. The traps may be avoided by injecting appropriate instructions into an instruction stream for execution.

Abstract: An "n" dimensional mesh-connected massively parallel processing system uses pointers to connect requesting processors to allocated processors, and also, to access the allocated processors. The requesting and allocated processors are connected by (i) storing in the requesting processor or in a system controller a pointer which points to the allocated processors as a group and (ii) storing in each of the allocated processors, in a designated memory location, an assigned-marker, or an identifier which identifies the processor as a member of the identified group. When one or more requesting processors require connection to free processors, a request is sent to each processor in the system asking each of them to determine if it is free. Each of the processors which is free then assigns itself indices relating to its position in the mesh and its position relative to other free processors.