Abstract: Disclosed embodiments provide methods, systems, and computer program products for process monitoring of interconnect wiring configurations and determining interconnect wiring characteristics including resistor-capacitator (RC) delay and capacitance parasitics of a given interconnect wiring configuration of a chip design. A disclosed interconnect monitor structure includes multiple stages, where each stage includes a source latch to receive scan test pattern input, a buffered wire segment including defined interconnect wire and threshold voltage configurations, and a capture latch capturing output test scan patterns. Disclosed test pattern generation implementations enable efficient and effective wiring interconnect process monitoring and identifying interconnect wiring characteristics and performance for an interconnect wiring configuration of a given IC design.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: Predicting failure in a circuit design caused by noise impact including receiving, for a net representing the circuit design and including at least one of a source or a sink gate, data for a specified feature set; predicting a failure related to noise impact including induced switching of the net based on the data for the specified feature set and using noise tolerance information; upon receiving the prediction, modifying the net using the predicted failure information; and after modifying the net using the predicted failure information, re-predicting a failure related to noise impact including induced switching of the net based on updated data for the specified feature set and using noise tolerance information; and upon receiving the updated prediction, modifying the net using the updated predicted failure information.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: A computer-implemented method includes receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip. Further, the method includes extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design. Further, the method includes predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block, the predicting performed using a pre-trained machine learning model. Further, the method includes using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: A computer-implemented method includes receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip. Further, the method includes extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design. Further, the method includes predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block, the predicting performed using a pre-trained machine learning model. Further, the method includes using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: The present invention describes methods for quantifying and analyzing cell migration and drug screening. Such methods include a gel (or a hydrogel) comprising a polymer, and cells that forms an oxygen gradient within the gel by controlling the balance of the diffusion of oxygen through the top of the gel and by the consumption of oxygen uptake by the cells. The migration of the cells is determined while the cells are grown in the gel of the present invention.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: A circuit-cycle fault reproduction system includes a hardware processor configured to execute at least one computing cycle corresponding to a given number instructions. A cycle tracking unit is configured to identify at least one test cycle included in a range of computing cycles starting from at a start cycle and completing at an end cycle. A fail cycle detection unit is in signal communication with the cycle tracking unit. The fail cycle detection unit is configured to identify a failed cycle among the plurality of test cycles based on a cycle difference between the starting cycle and the ending cycle, and to actively modify the range of computing cycles based on a comparison between the cycle difference and a cycle difference threshold value.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: A computer-implemented method for instruction-level tracing for analyzing processor failure includes detecting a failure during operation of a processor circuit. The method further includes parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure. The method further includes generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace. The method further includes performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times. The method further includes using the workload for debugging the failure based on the commit ratio being above a predetermined threshold.

Abstract: Managing system memory allocation according to a thermal profile defining memory segment policies according to power, performance, and thermal requirements, selecting a defined memory segment policy, implementing a system workload according to the memory segment policy and deploying the system workload according to the implemented memory segment policy.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: A non-transitory computer readable storage medium has instructions executed by a processor to supply text from a court decision. Indicia of the number of subsequent citations to the court decision are provided adjacent to the text. The indicia include at least one of a case citation count and associated visualization, a page citation count and associated visualization and page rank indicia.

Abstract: A computer-implemented method for instruction-level tracing for analyzing processor failure includes detecting a failure during operation of a processor circuit. The method further includes parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure. The method further includes generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace. The method further includes performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times. The method further includes using the workload for debugging the failure based on the commit ratio being above a predetermined threshold.

Abstract: Managing system memory allocation according to a thermal profile defining memory segment policies according to power, performance, and thermal requirements, selecting a defined memory segment policy, implementing a system workload according to the memory segment policy and deploying the system workload according to the implemented memory segment policy.