Abstract: A power supply including an inverter receiving a DC input signal from a DC input source (11). The inverter is implemented as a single-ended inverter. Each inverter is driven by a signal source (13A, 13B), which outputs an AC signal. The output from each inverter is input to a first stage harmonic filter. The power supply includes an output circuit that includes a rectifier (D1) arranged about a point so that if the inverter attempts to drive the point beyond a predetermined voltage, the rectifier conducts in order to return at least one of power and current to the DC input source. The output from the first harmonic filter (L1A, C1; L1B, C1) is output to a second harmonic filter (L2, C2) and is then output from the power supply.

Abstract: A scalable radio frequency (RF) generator system including at least one power supply, at least one power amplifier receiving input from the power supply, and a power supply control module, and a system controller. Output from the at least one power supply can be combined and applied to each of the power amplifiers. Output form each of the at least one power amplifiers can be combined to generate a single RF signal. A compensator module controls operation of the at least one power supply. The compensator module, system control module, and power supply controller communicate in a daisy chain configuration.

Abstract: A power supply including an inverter receiving a DC input signal from a DC input source (11). The inverter is implemented as a single-ended inverter. Each inverter is driven by a signal source (13A, 13B), which outputs an AC signal. The output from each inverter is input to a first stage harmonic filter. The power supply includes an output circuit that includes a rectifier (D1) arranged about a point so that if the inverter attempts to drive the point beyond a predetermined voltage, the rectifier conducts in order to return at least one of power and current to the DC input source. The output from the first harmonic filter (L1A, C1; L1B, C1) is output to a second harmonic filter (L2, C2) and is then output from the power supply.

Abstract: A method and apparatus is provided for passing an N bit wide data stream between two physical devices at high speed while maintaining the coherency of the data streams during the transfer. The N bit wide data stream is transmitted in N parallel data streams on N of N+1 differential data lines. A predetermined serial sync detect pattern is transferred on the remaining differential data line, which is designated as the sync line. A sub interval clock phase is then determined for the sync line that will successfully extract the transmitted sync detect pattern during each half cycle of the clock. This sub interval clock phase compensates for differing delays in the data streams across the physical interface. All of the N+1 differential data lines are in turn designated as the sync line to determine a sub interval clock phase for each of the respective differential data lines. Data is then extracted from the N data streams by sampling at the sub interval clock phase determined for each particular data line.