Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

Abstract: In one embodiment, an apparatus is provided. The apparatus includes a printed circuit board. The apparatus also includes a first connector coupled to the printed circuit board. The first connector is configured to couple the apparatus to a computing device. The apparatus further includes a second connector coupled to the printed circuit board. The second connector is configured to couple the apparatus to a data storage device. The apparatus further includes a securement mechanism comprising a first portion and a second portion. The securement mechanism is movable about the apparatus between a first position and a second position. The first portion is configured to maintain the securement mechanism at the first position. The second portion is configured to secure the data storage device to the apparatus when the securement mechanism is in the first position.

Abstract: A memory controller includes, in one embodiment, a memory interface and a dynamic stripe length manager circuit configured to receive a first weighted health factor associated with a first memory block of the memory, determine a first collective stripe length of the first memory block based on the first weighted health factor, set a first number of zones in the first memory block based on the first collective stripe length, monitor the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length, receive a second weighted health factor associated with the first memory block, determine the second collective stripe length based on the second weighted health factor, and set a second number of zones in the first memory block based on the second collective stripe length.

Abstract: A memory controller includes, in one embodiment, a memory interface and a dynamic stripe length manager circuit configured to receive a first weighted health factor associated with a first memory block of the memory, determine a first collective stripe length of the first memory block based on the first weighted health factor, set a first number of zones in the first memory block based on the first collective stripe length, monitor the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length, receive a second weighted health factor associated with the first memory block, determine the second collective stripe length based on the second weighted health factor, and set a second number of zones in the first memory block based on the second collective stripe length.

Abstract: A system and method for a power-cycle based read scrub of a memory device is provided. A controller stores an access counter which indicates a number of times a logical block address (LBA) has been accessed. When the LBA is accessed, the LBA counter is incremented. If the LBA counter indicates a count higher than a predetermined count, data stored in the LBA is duplicated and the duplicate data is stored as backup data. Subsequent access of the LBA will show that the LBA count is higher than the predetermined count, so the backup data will be accessed rather than the original LBA, thus preventing read-induced failure of the data which may be caused by further repeated access of the same LBA.

Abstract: A non-volatile storage apparatus receives first data from an entity external to the non-volatile storage apparatus, combines the first data with other data being stored in the non-volatile storage apparatus to create combined data, performs a programming process to program the first data into a first location, determines that the programming process failed, intentionally corrupts the first data programmed into the first location, recovers the first data from the combined data, and reprograms the recovered first into a second location.

Abstract: A method for detecting faults in a memory system includes performing an operation on at least one memory cell of the memory system. The method also includes receiving, during performance of the operation, a first clock cycle count for a first pulse of a charge pump associated with the at least one memory cell. The method also includes receiving, during performance of the operation, a second clock cycle count for a second pulse of the charge pump. The method also includes determining whether a fault will occur based on a difference between the first clock cycle count and the second clock cycle count.

Abstract: An apparatus includes non-volatile memory and a control circuit configured to program the non-volatile memory. The control circuit is configured to change a programming order. In one aspect, the control circuit changes the order in which word lines are programmed from one point in time to another. In one aspect, the control circuit uses one order for programming one set of word lines and a different order for a different set of word lines. The sets of word lines could be in different sub-blocks, memory blocks, or memory dies. Such programming order differences can improve performance of error recovery.

Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Abstract: A non-volatile storage apparatus receives first data from an entity external to the non-volatile storage apparatus, combines the first data with other data being stored in the non-volatile storage apparatus to create combined data, performs a programming process to program the first data into a first location, determines that the programming process failed, intentionally corrupts the first data programmed into the first location, recovers the first data from the combined data, and reprograms the recovered first into a second location.

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.

Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.