Abstract: In one embodiment, a subset of a set of streaming kernels of an application is selected for implementation on a reconfigurable processor. The streaming kernels are selected by first forming a stream flow graph of the application by parsing a program of instructions of the application, the stream flow graph having kernel nodes and edges, and determining benefit and cost values for each kernel node in the stream flow graph. Next, a subset of the kernel nodes that maximizes a weighted sum of the benefits values is selected, subject to a constraint that the sum of cost values is not greater than a prescribed value for the reconfigurable processor.

Abstract: A streaming data interface device (700) of a streaming processing system (200) is automatically generated by selecting a set of circuit parameters (610) consistent with a set of circuit constraints and generating (612, 614) a representation of a candidate memory interface device based upon a set of stream descriptors.

Abstract: A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation of a candidate streaming processor circuit based upon the set of circuit parameters to execute one or more iterations of a computation specified by a streaming data flow graph. The candidate streaming processor circuit is evaluated with respect to one or more quality metrics and the representation of the candidate streaming processor circuit is output if the candidate streaming processor circuit satisfies a set of processing system constraints and is better in at least one of the one or more quality metrics than other candidate streaming processor circuits.

Abstract: Bus transactions in a memory controller are scheduled by storing a set of configuration parameters that define a bus scheduling policy, generating values of a set of dynamic cost functions for each bus transaction, ordering the bus transactions in accordance with the bus scheduling policy to produce ordered bus transactions and generating a memory transaction that is derived from the ordered bus transactions. The memory controller includes one or more control registers for storing the set of configuration parameters, a bus interface operable to capture bus transactions from applications, a set of buffers operable to store the bus transactions and the set of dynamic cost functions and one or more registers operable to store the statistical data and a cost policy. The memory controller selects the order of the bus transactions based on an arbitration and selection policy and generates memory transactions to an external memory.

Abstract: A display apparatus 200, a display controller 222, and a method for optimizing a displayed image for use in an electronic device 100 comprising a display 208 for presenting a visual image, a processor 212 for determining the intensity of a backlight 216 used for illuminating the display 208 and a controller 202 that optimizes the visual image corresponding to the intensity of the backlight 216 are described. As the intensity of the backlight 216 is reduced, the brightness of the pixels 210 is increased to compensate the image when, for example, the backlight intensity is reduced to save power. The method and apparatus are also described for compensating for uneven backlight 216 conditions.

Abstract: A serial arbitration system utilizes an arbitration token containing a start bit, a request bit, a set of priority bits, and an error detection bit. The arbitration token is sent to each of the other processors (20, 21, 22) and is used to arbitrate control of a shared bus (38). A processor indicates that it is the master (20) by setting the start bit (120). It enters an arbitration by setting the request bit (124). The set of priority bits (134) contains a binary priority value encoded in bit major order. This format allows an optimized parallel comparison (128, 130) of the priority values for each of the requesting processors a bit at a time. Finally, processors drop out of the arbitration upon detecting (136) a parity error in an arbitration token received from another processor.

Abstract: A serial arbitration system for arbitration between multiple processors (20, 21, 22) in a low power system has an arbitration line driven by each of the processors and received by each of the other processors. The arbitration lines (30, 31, 32) are coupled to arbitration ports (60, 61, 62, 63, 64) on each processor (20, 21, 22) numbered from zero for the driven arbitration port (60). Each of the processors (20, 21, 22) has a processor ID number, with a master processor (20) having ID zero. The arbitration line (30) driven by the master processor (20) is coupled to each other processor (21, 22) on the arbitration port (61', 62') numbered equal to the processor ID of that other processor (21, 22). The driven arbitration lines (31, 32) from the other processors (21, 22) are coupled to the arbitration ports (61, 62) on the master processor (20) corresponding to the processor ID of the driving processor (21, 22).