Abstract: A spread spectrum clock signal generator modulates a reference clock signal based on a spread spectrum frequency profile and includes a phase-lock loop for generating a spread spectrum clock signal by aligning a phase of the modulated reference clock signal with a phase of the spread spectrum clock signal. The spread spectrum clock signal generator also includes a loop modulator for modulating the spread spectrum clock signal based on the spread spectrum frequency profile. Because the spread spectrum clock signal generator modulates both the reference clock signal and the spread spectrum clock signal based on the spread spectrum frequency profile, the spread spectrum clock signal has a non-distorted frequency profile and low phase jitter.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Abstract: A control circuit includes a phase frequency detector that receives a reference phase ?REF (signal) as an input and a feedback phase ?FBK (signal) as control feedback. A voltage controlled oscillator is in electrical communication with the phase frequency detector. The VCO provides an output and the feedback phase ?FBK (signal). An auxiliary feedback loop receives error phase ?E (signal) from each of the reference phase ?REF (signal) and the feedback phase ?FBK (signal). The auxiliary feedback loop provides an adjustment signal to the control circuit to correct for static phase offset.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Abstract: A control circuit includes a phase frequency detector that receives a reference phase ?REF (signal) as an input and a feedback phase ?FBK (signal) as control feedback. A voltage controlled oscillator is in electrical communication with the phase frequency detector. The VCO provides an output and the feedback phase ?FBK (signal). An auxiliary feedback loop receives error phase ?E (signal) from each of the reference phase ?REF (signal) and the feedback phase ?FBK (signal). The auxiliary feedback loop provides an adjustment signal to the control circuit to correct for static phase offset.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.

Abstract: A spread-spectrum modulation method and circuit for a clock generator phase-locked loop (PLL). A dither signal is injected into a PLL in synchronization with and having the same period or fraction of the same period as the phase comparison performed within the PLL. Over such period, the phase error caused by the modulation will integrate to zero and hence avoid transmitting a disturbance to the loop. A particular embodiment utilizes an output of the reference divider and/or feedback divider within the PLL to generate the dither signal. Such a configuration avoids the need for additional hardware which otherwise would increase the chip area and/or cost of the device. The reference divider and/or feedback divider is made up preferably of a linear feedback shift register (LFSR). One or more stages of the LFSR provide an output which is used to generate the dither signal. In a preferred embodiment, the output from the LFSR exhibits a pseudo-random sequence.

Abstract: A voltage controlled oscillator having substantial frequency dependence on a parallel RC timing element including a voltage-variable resistance element, such as a MOSFET biased in the triode region. One terminal of the timing element can be connected to ground. The voltage used to tune the timing element, to lock the voltage controlled oscillator to a reference frequency can be used to control similar timing elements integrated upon the same circuit, for example a continuous-time filter in an ethernet transceiver. The oscillator frequency is substantially independent of variations in supply voltage.

Abstract: A video dot clock generator includes a phase-locked loop (PLL) which includes a voltage controlled oscillator, a frequency divider, a phase comparator and a loop filter. The voltage controlled oscillator (VCO) is programmable to provide multiple frequency ranges for a given range of control voltages applied to the oscillator. The programming affects both the frequency range and the gain of the VCO. The phase comparator includes circuitry which simulates a predetermined minimum phase error which, when compensated for, substantially eliminates jitter in the dot clock signal. The frequency divider used in the PLL and a similar frequency divided used to generate the reference signals for the phase comparator are programmable via an internal memory which also holds programmable control signals for the VCO. The memory, in turn, may be programmed by the user to achieve desired frequency and loop again characteristics for a given application.

Abstract: A linear variable differential transformer pressure transducer includes a pressure sensing element which is deformed in response to changes in the pressure of a fluid. The pressure sensing element is connected to the core of a differential transformer, the coils of which are mounted on a dashpot within which the core is disposed. The dashpot is filled with a damping fluid which surrounds the core. The core enters the dashpot through an opening in a flexible boot which covers the open end of the dashpot to prevent leakage of the damping fluid. The pressure transducer serves to suppress destructive harmonic resonances of the Bourdon tube by imparting a variable restraining force on the linear movement of the core. The pressure transducer exerts a minimal restraining force to the low frequency movements of the core caused by normal fluctuations in the fluid pressure, but exerts a high restraining force against sudden pressure transients or vibration near the pressure sensing element's resonant frequency.