Abstract: A testing backplane apparatus includes first test ports configured to receive a first processor assembly under test and the plurality of first test ports may be an even number of first test ports or an odd number of first test ports. The testing backplane apparatus includes second test ports, where each first test port corresponds to a second test port and the second test ports connect to a second processor assembly. The testing backplane apparatus includes a signal pathway from each first test port to a second test port. The signal pathway includes a signal path length within a range between a maximum signal path length and a minimum signal path length. Each port on the first processor assembly corresponds to each port on the second processor assembly and the testing backplane apparatus is configured differently from a backplane used as a final destination for operating the first processor assembly.

Abstract: According to one embodiment of the present disclosure, hardware initialization code and error action information are retrieved from separate storage areas. The hardware initialization code includes code that initializes a device, and also includes placeholders corresponding to actions that are performed when the device fails initialization. Likewise, the error action information describes the actions that are performed when the device fails initialization. The error action information is converted into macros that include lines of code. As such, the error action placeholders are matched to the macros and, in turn, each of the error action placeholders is replaced with the lines of code corresponding to the matched macros.

Abstract: A testing backplane apparatus includes first test ports configured to receive a first processor assembly under test and the plurality of first test ports may be an even number of first test ports or an odd number of first test ports. The testing backplane apparatus includes second test ports, where each first test port corresponds to a second test port and the second test ports connect to a second processor assembly. The testing backplane apparatus includes a signal pathway from each first test port to a second test port. The signal pathway includes a signal path length within a range between a maximum signal path length and a minimum signal path length. Each port on the first processor assembly corresponds to each port on the second processor assembly and the testing backplane apparatus is configured differently from a backplane used as a final destination for operating the first processor assembly.

Abstract: According to one embodiment of the present disclosure, hardware initialization code and error action information are retrieved from separate storage areas. The hardware initialization code includes code that initializes a device, and also includes placeholders corresponding to actions that are performed when the device fails initialization. Likewise, the error action information describes the actions that are performed when the device fails initialization. The error action information is converted into macros that include lines of code. As such, the error action placeholders are matched to the macros and, in turn, each of the error action placeholders is replaced with the lines of code corresponding to the matched macros.

Abstract: Performance in object-oriented systems may be improved by allowing multiple concurrent hardware control and diagnostic operations to run concurrently on the system while preventing race conditions, state/data corruption, and hangs due to deadlock conditions. Deadlock prevention rules may be employed to grant or deny request for hardware operation locks, hardware communication locks, and/or data locks.

Abstract: According to one embodiment of the present disclosure, hardware initialization code and error action information are retrieved from separate storage areas. The hardware initialization code includes code that initializes a device, and also includes placeholders corresponding to actions that are performed when the device fails initialization. Likewise, the error action information describes the actions that are performed when the device fails initialization. The error action information is converted into macros that include lines of code. As such, the error action placeholders are matched to the macros and, in turn, each of the error action placeholders is replaced with the lines of code corresponding to the matched macros.

Abstract: According to one embodiment of the present disclosure, hardware initialization code and error action information are retrieved from separate storage areas. The hardware initialization code includes code that initializes a device, and also includes placeholders corresponding to actions that are performed when the device fails initialization. Likewise, the error action information describes the actions that are performed when the device fails initialization. The error action information is converted into macros that include lines of code. As such, the error action placeholders are matched to the macros and, in turn, each of the error action placeholders is replaced with the lines of code corresponding to the matched macros.

Abstract: A mechanism is provided for monitoring and verifying a clock state of a chip that does not write out clock state information. Responsive to identifying an access to the chip, the access is scanned to identify a chip register and a clock domain that will be accessed. A determination is made as to whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit. Responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, the clock state from the logical clock state unit is identified. Responsive to the clock state matching the clock state required by the access, the access is forwarded to the chip for execution.

Abstract: A mechanism is provided for monitoring and verifying a clock state of a chip that does not write out clock state information. Responsive to identifying an access to the chip, the access is scanned to identify a chip register and a clock domain that will be accessed. A determination is made as to whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit. Responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, the clock state from the logical clock state unit is identified. Responsive to the clock state matching the clock state required by the access, the access is forwarded to the chip for execution.

Abstract: A mechanism is provided for recovering from a data scan error. A service processor determines the nature of the data scan error and, depending on the nature of the error, performs one of a plurality of data scan error recovery procedures.

Abstract: Performance in object-oriented systems may be improved by allowing multiple concurrent hardware control and diagnostic operations to run concurrently on the system while preventing race conditions, state/data corruption, and hangs due to deadlock conditions. Deadlock prevention rules may be employed to grant or deny request for hardware operation locks, hardware communication locks, and/or data locks.

Abstract: According to a method of data processing in a data processing system, a hardware management component receives from a software component of the data processing system a request for management access to a hardware component of the data processing system. In response to receipt of the request for management access, the hardware management component determines whether or not the request contains a parameter indicative of the intended scope of hardware components to be accessed in response to the request. In response to the request, the hardware management component selects a scope in accordance with the determination and issues one or more hardware management commands to one or more target hardware components of the data processing system within the selected scope, such that an operating state of the one or more target hardware components is modified.

Abstract: Systems, methods and media for recovering from a data scan error are disclosed. In one embodiment, a service processor determines the nature of the data scan error and, depending on the nature of the error, performs one of a plurality of data scan error recovery procedures.

Abstract: According to a method of data processing in a data processing system, a hardware management component receives from a software component of the data processing system a request for management access to a hardware component of the data processing system. In response to receipt of the request for management access, the hardware management component determines whether or not the request contains a parameter indicative of the intended scope of hardware components to be accessed in response to the request. In response to the request, the hardware management component selects a scope in accordance with the determination and issues one or more hardware management commands to one or more target hardware components of the data processing system within the selected scope, such that an operating state of the one or more target hardware components is modified.

Abstract: Methods, articles of manufacture, and systems for software simulation of hardware, for use in testing firmware, are provided. The software simulation may be accomplished through the creation and use of a set of intelligent buffer objects (hereinafter “smart buffers”) corresponding to registers (e.g., status, control, and results registers) in actual hardware targeted by the firmware. When accessed, the smart buffers may call specialized functions (or behavior actions) designed to simulate (expected or unexpected) behavior of the targeted hardware by modifying smart buffers associated with the same or other hardware registers. The simulated behavior of the hardware may allow the firmware code to be properly exercised as if running on an actual product platform.

Abstract: Methods, articles of manufacture, and systems for software simulation of hardware, for use in testing firmware, are provided. The software simulation may be accomplished through the creation and use of a set of intelligent buffer objects (hereinafter “smart buffers”) corresponding to registers (e.g., status, control, and results registers) in actual hardware targeted by the firmware. When accessed, the smart buffers may call specialized functions (or behavior actions) designed to simulate (expected or unexpected) behavior of the targeted hardware by modifying smart buffers associated with the same or other hardware registers. The simulated behavior of the hardware may allow the firmware code to be properly exercised as if running on an actual product platform.