Abstract: A high performance disk subsystem has a disk write mechanism that provides high throughput for random disk writes by dividing the disks into a data portion and a log portion. A fault-tolerant memory in the disk controller is used to temporarily store data blocks or pages which are to be written in the data portion of the disks. The updated blocks are sorted in the fault-tolerant memory in accordance with their physical home location on the data portion of the disks. Sorted runs are temporarily written out to the log portion of the disk. In a parallel process, sorted runs are retrieved from the log portion of the disks, merged in the fault-tolerant memory, and written out to their home location on the data portion of the disks, which converts random disk writes to largely sequential I/O while retaining physical clustering of the data on disk.

Abstract: A fault-tolerant high performance mirrored disk subsystem is described which has an improved disk writing scheme that provides high throughput for random disk writes and at the same time guarantees high performance for disk reads. The subsystem also has an improved recovery mechanism which provides fast recovery in the event that one of the mirrored disks fails and during such recovery provides the same performance as during non-recovery periods.Data blocks or pages which are to be written to disk are temporarily accumulated and sorted (or scheduled) into an order (or schedule) which can be written to disk efficiently, which in a preferred embodiment is in accordance with the physical location on disk at which each such block will be written. This also generally corresponds to an order which is encountered by a writ head during a physical scan of a disk. The disks of a mirrored pair are operated out of phase with each other, so that one will be in read mode while the other is in write mode.

Abstract: An apparatus, embodied in an Intelligent Page Store, for providing concurrent and consistent access to a functionally separate transaction entity and a query entity to a shared database, while maintaining a single physical copy of most of the data. The Intelligent Page Store contains shared disk storage, and an intelligent versioning mechanism allows simultaneous access by the transaction entity and the query entity to the shared data. The transaction entity is presented the current data and the query entity is presented a recent and consistent version of the data. A single copy of all but recently updated pages is maintained by the Intelligent Page Store. The query and transaction entities operate independently of each other and are separately optimized.

Abstract: A multiprocessor system linked by a fiber optic ring network uses some of the bandwith of the ring network as a shared memory resource. Data slots are defined on the network which can carry message packets from one processor to another or network memory packets which circulate indefinitely on the network. One use of these network memory packets is as a lock management system for controlling concurrent access to a shared database by the multiple processors. The network memory packets are treated as lock entities. A processor indicates that it wants to procure a lock entity by circulating a packet, having a first network memory type, around the network. If no conflicting packets are detected when the circula ted packet returns, the type of the slot is changed to a second network memory type indicating a procured lock entity.

Abstract: A multi-processor computer system in which each processor is under the control of separate system software and access a common database. A two level lock management system is used to prevent data corruption due to unsychronized data access by the multiple processors. By this system, subsets of data in the database are assigned respectively different lock entities. Before a task running on one of the processors access data in the database it first requests permission to access the data in a given mode with reference to the appropriate lock entity. A first level lock manager handles these requests synchronously, using a simplified model of the locking system having shared and exclusive lock modes to either grant or deny the request. All requests are then forwarded to a second level lock manager which grants or denies the request based on a more robust model of the locking system and queues denied requests.

Abstract: A technique for performing joins in parallel on a multiple processor database system effectively deals with data skew. The join operation is performed in three stages with an optional fourth stage. The first stage is a preparatory stage, the detail of which depends on the underlying join algorithm used. This preparatory stage provides pre-processing the results of which are used in the following stage as the basis for defining subtasks for the final join operation. The data provided in the first stage is used in the second stage to both define subtasks and to optimally allocate these subtasks to different processors in such a manner that the processors are close to equally loaded in the final join operation, even in the presence of data skew. This second stage is an assignment stage the details of which depend on the underlying join algorithm.

Abstract: A modular fail-safe memory and an address generation mechanism that provides load balancing when the memory is shared by a number of processors. A plurality of memory modules are used for the memory with no specific limit on the number of memory modules, and a checksum block is used to back-up corresponding blocks in the other memory modules. The checksum blocks are distributed across the memory modules, and an address generation mechanism determines the checksum location for a specific memory block. This address generation mechanism ensures that checksum blocks are equally divided between the memory modules so that there is no memory bottleneck, is easy to implement in hardware, and is extended to provide similar properties when a module failure occurs.

Abstract: A method of switching data packets through a multistage interconnection network (MIN), to prevent hot spot traffic from degrading uniform traffic performance. Each of the address bits in each packet determine the output link at each particular stage of the network to which the packet must be routed. A packet is accepted at an input buffer of the stage only if an acceptance test is met. This acceptance test depends not only on the availability of a buffer at the input buffer at a stage of the network, but also on how the address bits of the packet are related to address bits of other packets in the buffer, and on the stage of the network. If the acceptance test is not met, the packet is retained in the previous stage of the MIN, and is moved to the rear of a queue of packets in the buffer at that stage, or given a lower priority in the queue.

Abstract: This invention relates to a method of switching voice and data over a multistage interconnection network (MIN). More specifically, a plurality of bits are stored in respective storage locations of the switching elements of the MIN. Storage location of a switching element represents a particular time slot in a frame or a sequence of frames. Bits stored in each location represent specific conditions of the inputs and outputs of the switching elements and also indicate which inputs of the switching elements will be connected to which outputs of the switching elements. This storage of control information in the switching elements allows the switching network to rapidly and simultaneously change connections through the switching elements of the network.

Abstract: In a communication system comprising several stations, access to the ring is granted to one station at a time by circulating a token on the ring and updating the priority of the token is disclosed. This invention provides for a first station to transmit a token immediately after it has finished transmitting a frame containing a packet(s) needed to be transmitted from the first station without waiting for the header of the frame to return to the first station. A priority signalling packet is then transmitted on the ring from the first station after the first station transmits the token on the ring. This priority signalling packet contains information as to the particular priority level that the token should be updated to. Finally, the priority level of the token is updated to correspond to the particular priority level when the priority signalling packet reaches the station that holds the token.

Abstract: A method of switching synchronous and asynchronous data packets through a multi-stage interconnection network (MIN), so as to insure that packets with the highest assignable priority level will never be blocked at any stage of the network. More specifically, this invention relates to a method of switching voice and data packets over the MIN wherein each of the address bits in each packet determine the connection to be established at each particular stage in the network and wherein each packet has therein a priority level. In each time slot of a frame, the priority level of the packets stored in a particular originating adapter are compared and the packet with the highest priority level in each adapter is forwarded through the MIN and routed through the MIN as described above. Also, at each subswitch at each stage of the MIN, if two or more packets request the same subswitch output, only the packet with the higher priority is forwarded to the subswitch output.