Patents by Inventor Daniel M. Dosado

Daniel M. Dosado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of converting a serial vector format (SVF) file to a vector compatible with a semiconductor testing system
    Patent number: 11747400
    Abstract: Provided is a method for enabling a semiconductor test system for testing field programmable gate arrays (FPGAs) to operate as a device programmer by converting a serial vector format (SVF) file containing a bitstream and converting the file to a vector compatible with the semiconductor test system. When executed on an HP93K test system, as an example, the vector generates JTAG (Joint Test Action Group) signals, which program the bitstream into a Field Programmable Gate Array (FPGA). The inventive method eliminates the need for a separate computer system that is normally required to run FPGA programming software and also eliminates the need to use FPGA vendor provided JTAG programming pods. Eliminating the need for the vendor software, a separate computer system, and programming pods reduces equipment cost, maintenance, and streamlines the electrical test, evaluation, and characterization of FPGAs.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: September 5, 2023
    Assignee: The United States of America, as Represented by the Secretary of the Navy
    Inventor: Daniel M. Dosado
  • METHOD OF CONVERTING A SERIAL VECTOR FORMAT (SVF) FILE TO A VECTOR COMPATIBLE WITH A SEMICONDUCTOR TESTING SYSTEM
    Publication number: 20230027456
    Abstract: Provided is a method for enabling a semiconductor test system for testing field programmable gate arrays (FPGAs) to operate as a device programmer by converting a serial vector format (SVF) file containing a bitstream and converting the file to a vector compatible with the semiconductor test system. When executed on an HP93K test system, as an example, the vector generates JTAG (Joint Test Action Group) signals, which program the bitstream into a Field Programmable Gate Array (FPGA). The inventive method eliminates the need for a separate computer system that is normally required to run FPGA programming software and also eliminates the need to use FPGA vendor provided JTAG programming pods. Eliminating the need for the vendor software, a separate computer system, and programming pods reduces equipment cost, maintenance, and streamlines the electrical test, evaluation, and characterization of FPGAs.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 26, 2023
    Applicant: The United States of America, as represented by the Secretary of the Navy
    Inventor: Daniel M. Dosado