Patents by Inventor Daniel M. McCarthy

Daniel M. McCarthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190308836
    Abstract: A registration system for a printing device and a method for controlling the same are disclosed. For example, the registration system includes at least one sensor to detect a position of a print media, a platform comprising at least one multi-rotational wheel, and a processor communicatively coupled to the at least one sensor and the at least one multi-rotational wheel, wherein the processor calculates a desired movement of the at least one multi-rotational wheel based on the position of the print media.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 10, 2019
    Inventors: Jacob R. McCarthy, Timothy D. Slattery, Joseph M. Ferrara, JR., James L. Pratt, Dara N. Lubin, Ron Edward Dufort, Elizabeth M. Crossen, Daniel M. McHugh, Rachel Lynn Bierasinski, Frank Berkelys Tamarez Gomez, Paul M. Fromm, Erwin Ruiz
  • Patent number: 10360162
    Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 23, 2019
    Assignee: NXP USA, Inc.
    Inventors: Daniel M. McCarthy, Joseph C. Circello, Kristen A. Hausman
  • Publication number: 20190190555
    Abstract: An apparatus and method for active noise cancellation, including but not limited to, noise cancellation at VLF frequencies. The invention facilitates the reception of critical information in variable and extreme EMI scenario with no information about the signal of interest. The invention utilizes an automated, signal agnostic active noise cancellation technique and associated hardware components. In order to extract the signal of interest, vector modulation is employed to the signal from the noise only antenna so as to match it and then subtract it from the received signal containing combined noise and signal of interest. This apparatus and method ensures that a signal of interest can be extracted from an extremely noisy environment without any knowledge about the characteristics of that signal.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: DEAN A PASCHEN, DANIEL F MCCARTHY, DONALD A HUEBNER, NATHAN M DEBARD
  • Patent number: 10073797
    Abstract: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: September 11, 2018
    Assignee: NXP USA, Inc.
    Inventors: Joseph C. Circello, Ujwala R. Malwade, Daniel M. McCarthy
  • Patent number: 10002076
    Abstract: A method includes generating least-recently-used location information for a shared set-associative multi-access cache and next-to least-recently-used location information for the shared set-associative multi-access cache. The method includes concurrently accessing a shared set-associative multi-access cache in response to a first memory request from a first memory requestor and a second memory request from a second memory requestor based on the least-recently-used location information and the next-to least-recently-used location information. The method may include updating the least-recently-used location information and the next-to least-recently-used location information in response to concurrent access to the shared set-associative multi-access cache according to the first memory request and the second memory request.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: June 19, 2018
    Assignee: NXP USA, Inc.
    Inventor: Daniel M. McCarthy
  • Patent number: 9824242
    Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, John D. Mitchell, Peter J. Wilson, John J. Vaglica
  • Publication number: 20170242803
    Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 24, 2017
    Inventors: Daniel M. McCarthy, Joseph C. Circello, Kristen A. Hausman
  • Patent number: 9672164
    Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: June 6, 2017
    Assignee: NXP USA, INC.
    Inventors: Daniel M. McCarthy, Joseph C. Circello, Kristen A. Hausman
  • Publication number: 20170091096
    Abstract: A method includes generating least-recently-used location information for a shared set-associative multi-access cache and next-to least-recently-used location information for the shared set-associative multi-access cache. The method includes concurrently accessing a shared set-associative multi-access cache in response to a first memory request from a first memory requestor and a second memory request from a second memory requestor based on the least-recently-used location information and the next-to least-recently-used location information. The method may include updating the least-recently-used location information and the next-to least-recently-used location information in response to concurrent access to the shared set-associative multi-access cache according to the first memory request and the second memory request.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Daniel M. MCCARTHY
  • Patent number: 9489316
    Abstract: Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, David J. Schimke
  • Publication number: 20150332069
    Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
    Type: Application
    Filed: July 27, 2015
    Publication date: November 19, 2015
    Inventors: Joseph C. Circello, Daniel M. McCarthy, John D. Mitchell, Peter J. Wilson, John J. Vaglica
  • Patent number: 9092647
    Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, John D. Mitchell, Peter J. Wilson, John J. Vaglica
  • Publication number: 20140281137
    Abstract: Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Joseph C. Circello, Daniel M. McCarthy, David J. Schimke
  • Publication number: 20140259149
    Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Inventors: Joseph C. Circello, Daniel M. McCarthy, John D. Mitchell, Peter J. Wilson, John J. Vaglica
  • Publication number: 20130326193
    Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Inventors: DANIEL M. MCCARTHY, Joseph C. Circello, Kristen A. Hausman
  • Patent number: 8417924
    Abstract: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: April 9, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, David J. Schimke
  • Patent number: 8312253
    Abstract: In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit device. The CPU is continually halted as the trace buffer is filled to facilitate retrieving all information written to the trace buffer.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: November 13, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, Sylvia M. Thirtle
  • Publication number: 20090217010
    Abstract: In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit device. The CPU is continually halted as the trace buffer is filled to facilitate retrieving all information written to the trace buffer.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 27, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, Sylvia M. Thirtle
  • Publication number: 20090217298
    Abstract: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 27, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Joseph C. Circello, Ujwala R. Malwade, Daniel M. McCarthy
  • Publication number: 20090217011
    Abstract: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 27, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, David J. Schimke