Abstract: According to an embodiment disclosed herein, a microelectronic device to be encapsulated is built on, or alternatively in, a substrate. The device is then coated with a sacrificial layer. A lid layer is deposited over the sacrificial layer, and then appropriately perforated to optimize the removal of the sacrificial layer. The sacrificial layer is then removed using one of several etching or other processes. The perforations in the lid layer are then sealed using a viscous sealing material, thereby fixing the environment that encapsulates the device. The sealing material is then cured or hardened. An optional moisture barrier may be deposited over the cured sealing layer to provide further protection for the encapsulation if needed.

Abstract: According to an embodiment disclosed herein, a microelectronic device to be encapsulated is built on, or alternatively in, a substrate. The device is then coated with a sacrificial layer. A lid layer is deposited over the sacrificial layer, and then appropriately perforated to optimize the removal of the sacrificial layer. The sacrificial layer is then removed using one of several etching or other processes. The perforations in the lid layer are then sealed using a viscous sealing material, thereby fixing the environment that encapsulates the device. The sealing material is then cured or hardened. An optional moisture barrier may be deposited over the cured sealing layer to provide further protection for the encapsulation if needed.

Abstract: According to an embodiment disclosed herein, a microelectronic device to be encapsulated is built on, or alternatively in, a substrate. The device is then coated with a sacrificial layer. A lid layer is deposited over the sacrificial layer, and then appropriately perforated to optimize the removal of the sacrificial layer. The sacrificial layer is then removed using one of several etching or other processes. The perforations in the lid layer are then sealed using a viscous sealing material, thereby fixing the environment that encapsulates the device. The sealing material is then cured or hardened. An optional moisture barrier may be deposited over the cured sealing layer to provide further protection for the encapsulation if needed.

Abstract: A method for creating and preserving alignment marks used for aligning mask layers in integrated circuit formation including the steps of creating a first set of marks within a reference layer to form a basic alignment mark, creating a second set of marks overlapping the first set of marks and positioned perpendicular to the first set of marks in the same reference layer to form a preservation pattern, and etching the reference layer to form a substantially checkerboard-type pattern where portions of the first set of marks are recessed within a thickness of the reference layer. After creating the checkerboard-type pattern formed from the first and second marks, a first metal a layer may be deposited to fill in any recesses contained within the pattern. CMP follows without damaging the segmented portions of the first set of marks which lie recessed within a thickness of the reference layer. Finally, the preserved portions of the first set of marks are aligned with pattern marks for a second metal layer.