Abstract: A synchronization mechanism is disclosed for controlling devices or sub-systems connected to a common bus in a multiprocessing system so that the devices are kept in step one with the other when performing sequences of operations. More specifically, the mechanism ensures that no device can start its (i+1)th operation until all devices have completed their ith operation. This is achieved by providing each device with three synchronizing logic blocks (LB1, LB2, LB3) (LB', LB2', LB3') each of which functions to generate control signals (p, q, r respectively) on associated control lines at the end of selected operations in the sequence of operations. The control lines monitoring the performance of corresponding operations in all the devices are each applied via logic circuits (L1 or L2 or L3 as appropriate) (L1' or L2' or L3') to one of three selected bus lines (P, Q, R respectively).

Abstract: In a system including several devices connected by means of a common data bus the adverse effects of reflections due to two or more devices simultaneously seeking access to the bus are minimized by confining such reflections to parts of the bus remote from the devices. This is achieved by preventing the amplitude of a signal at a receiving station on the bus from exceeding a predetermined level; and integrated circuit serving as a near ideal diode clamped to a reference voltage performs this function.