Patents by Inventor Daniel Maassen

Daniel Maassen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250105799
    Abstract: Example embodiments relate to compact Doherty amplifiers having improved video bandwidth. One example embodiment includes an amplifier. The amplifier includes a package having a substrate. The amplifier also includes at least one amplifier unit arranged in the package. Each amplifier unit includes an input terminal and an output terminal. Each amplifier unit also includes an active semiconductor die on which a high-power transistor is integrated. Additionally, each amplifier unit includes an input matching capacitor and an output matching capacitor. Further, each amplifier unit includes a third inductor connecting an output of the high-power transistor to the output matching capacitor. In addition, each amplifier unit includes a fourth inductor connecting an input of the high-power transistor to the input matching capacitor. Yet further, each amplifier unit includes an output resonance network including a series connection of a first inductor and a first capacitor.
    Type: Application
    Filed: January 30, 2023
    Publication date: March 27, 2025
    Inventor: Daniel Maassen
  • Publication number: 20250062220
    Abstract: Example embodiments relate to vertically stacked capacitors. One capacitor assembly includes a vertical stacking of a first capacitor and a second capacitor on a substrate. The first capacitor includes a first terminal and a second terminal. The second terminal is formed by a first conductive layer that includes stress relief openings. The second capacitor includes a first terminal and a second terminal. The second terminal of the first capacitor lies below the first terminal of the first capacitor. The second terminal of the second capacitor lies below the first terminal of the second capacitor. The second capacitor lies below the first capacitor. The capacitor assembly further includes a ground layer. The second terminal of the second capacitor is electrically connected to the ground layer and to the first conductive layer. The ground layer includes stress relief openings. The ground layer is configured to be electrically grounded during operation.
    Type: Application
    Filed: August 15, 2024
    Publication date: February 20, 2025
    Inventors: Daniel Maassen, Bart Van Velzen
  • Patent number: 12142583
    Abstract: Example embodiments relate to RF amplifier packages. One example RF amplifier package includes an input terminal, an output terminal, a substrate, a first DC blocking capacitor having a first terminal and a grounded second terminal, and a second conductor die mounted on the substrate. The semiconductor die includes a semiconductor substrate, an RE power field-effect transistor (FET) integrated on the semiconductor substrate, a gate bondbar, a first drain bondbar, a second drain bondbar, and a plurality of first bondwires connecting the second drain bondbar to the first terminal of the first DC blocking capacitor. The RF power FET includes a plurality of gate fingers that are electrically connected to the gate bondbar and that each extend from the gate bondbar towards the first drain bondbar and underneath the second drain bondbar, a first set of drain fingers, and a second set of drain fingers.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: November 12, 2024
    Assignee: Ampleon Netherlands B.V.
    Inventors: Josephus Henricus Bartholomeus Van der Zanden, Daniel Maassen
  • Publication number: 20240080003
    Abstract: Example embodiments relate to digital RF amplifiers. One example digital RF amplifier includes a driver having a plurality of outputs and being configured to individually set a signal level at the outputs either to an inactive or active level in response to a digital input signal. The RF amplifier also includes a transistor configured to output an analog RF signal at a transistor output. The transistor includes a plurality of transistor cells, each including a control terminal, an output terminal, and a common terminal. The transistor also includes a plurality of transistor inputs, each transistor input being electrically connected to the control terminal of at least one transistor cell. The transistor inputs are mutually electrically isolated. Each transistor input is connected to a different output of the driver. The transistor output is electrically connected to the output terminals of the plurality of transistor cells. The transistor is a circular transistor.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 7, 2024
    Inventors: Johannes Adrianus Maria De Boet, Daniel Maassen, Rob Mathijs Heeres
  • Publication number: 20220173057
    Abstract: Example embodiments relate to RF amplifier packages. One example RF amplifier package includes an input terminal, an output terminal, a substrate, a first DC blocking capacitor having a first terminal and a grounded second terminal, and a second conductor die mounted on the substrate. The semiconductor die includes a semiconductor substrate, an RE power field-effect transistor (FET) integrated on the semiconductor substrate, a gate bondbar, a first drain bondbar, a second drain bondbar, and a plurality of first bondwires connecting the second drain bondbar to the first terminal of the first DC blocking capacitor. The RF power FET includes a plurality of gate fingers that are electrically connected to the gate bondbar and that each extend from the gate bondbar towards the first drain bondbar and underneath the second drain bondbar, a first set of drain fingers, and a second set of drain fingers.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 2, 2022
    Inventors: Josephus Henricus Bartholomeus Van der Zanden, Daniel Maassen