Abstract: The invention relates to a circuit arrangement, comprising: a functional circuit with m (m=1, 2, . . . ) data inputs and n (n=1, 2, . . . ) data outputs for processing at least one m-dimensional binary data input (x1, . . . , xm) to form an n-dimensional data output (y1, . . . , yn), wherein the functional circuit comprises at least one combinatorial circuit part, at least two registers with a word length k (k=1, 2, . . . ; k?n) which are coupled to at least some of the n data outputs of the functional circuit in order to store output values (y=y1, . . . , yk; y?=y?1, . . . , y?k) which are duplicated with respect to one another or are duplicated with bit-by-bit inversion with respect to one another, said output values being derived from the n-dimensional data output (y1, . . .

Abstract: The invention relates to a circuit arrangement, comprising: a functional circuit with m (m=1, 2, . . . ) data inputs and n (n=1, 2, . . . ) data outputs for processing at least one m-dimensional binary data input (x1, . . . , xm) to form an n-dimensional data output (y1, . . . , yn), wherein the functional circuit comprises at least one combinatorial circuit part, at least two registers with a word length k (k=1, 2, . . . ; k?n) which are coupled to at least some of the n data outputs of the functional circuit in order to store output values (y=y1, . . . , yk; y?=y?1, . . . , y?k) which are duplicated with respect to one another or are duplicated with bit-by-bit inversion with respect to one another, said output values being derived from the n-dimensional data output (y1, . . .