Abstract: An apparatus includes a power converter having a first voltage terminal and a second voltage terminal and including a voltage divider coupled between the second voltage terminal and a voltage supply terminal. The voltage divider has an output. A transconductance amplifier has a first input, a second input, and an output. The first input is coupled to the output of the voltage divider. The second input is coupled to a reference voltage circuit. A first capacitor is coupled between the output of the transconductance amplifier and the voltage supply terminal. A buffer has an input coupled to the output of the transconductance amplifier and has an output. A second capacitor is coupled between the output of the buffer and the second voltage terminal.

Abstract: Aspects of the present disclosure provide for circuit. In at least some examples, the circuit includes a controller, a current source, a switch, and a digital-to-analog converter (DAC). The controller includes an analog-to-digital converter (ADC) having an input and an output, a first register, and a second register coupled to the output of the ADC. The switch is coupled between an output of the current source and a first node and has a control terminal coupled to the controller. The first node is coupled to the input of the ADC and is configured to couple to a resistor. The DAC has an input coupled to the controller and an output configured to couple to a battery.

Abstract: Aspects of the present disclosure provide for circuit. In at least some examples, the circuit includes a controller, a current source, a switch, and a digital-to-analog converter (DAC). The controller includes an analog-to-digital converter (ADC) having an input and an output, a first register, and a second register coupled to the output of the ADC. The switch is coupled between an output of the current source and a first node and has a control terminal coupled to the controller. The first node is coupled to the input of the ADC and is configured to couple to a resistor. The DAC has an input coupled to the controller and an output configured to couple to a battery.

Abstract: Systems and methods for bit stuffing pulse width modulation are provided. Example embodiments of the systems and methods of bit stuffing pulse width modulation disclosed herein may allow for a significant reduction in the size of the bootstrap capacitor while giving up only a small percentage of output drive, and reduce die space. Included in such systems and methods is the ability to digitally detect inactivity on the PMW signals for a class D power amplifier, and to digitally insert small charge pulses at a fairly low repetition rate relative to the normal switching frequency. The low repetition rate may preserve the maximum output power while still allowing enough charge to transfer to the bootstrap capacitor.

Abstract: Systems and methods for bit stuffing pulse width modulation are provided. Example embodiments of the systems and methods of bit stuffing pulse width modulation disclosed herein may allow for a significant reduction in the size of the bootstrap capacitor while giving up only a small percentage of output drive, and reduce die space. Included in such systems and methods is the ability to digitally detect inactivity on the PMW signals for a class D power amplifier, and to digitally insert small charge pulses at a fairly low repetition rate relative to the normal switching frequency. The low repetition rate may preserve the maximum output power while still allowing enough charge to transfer to the bootstrap capacitor.

Abstract: A closed loop audio amplifier system and method of powering up/down the system without producing audible artifacts are provided. During power up, a prebias voltage is provided to each output connected to a speaker to increase the voltage to a nominal output level. High impedance switches are then driven at a 50% duty cycle. Feedback from the output is supplied to a servo, which is enabled to fine tune the output voltage. Low impedance switches are then driven at a 50% duty cycle at a quarter cycle timing. The order of the feedback loop depends on which of the high or low impedance switches are driven. The prebias voltage is then removed before audio signals to be amplified are supplied to the system. Timing of driving of the switches is programmable. To power down,. essentially the reverse sequence is provided.

Abstract: An improved bias network for reducing cross-over distortion in a device having complementary p-MOS and n-MOS power transistors includes complementary helper transistors coupled to power transistors for discharging currents while the power transistors are biased in sub-threshold regions of operation. The bias network further includes complementary resistors coupled to the power transistors for biasing the power transistors within saturation regions of operation and for biasing the helper transistors within saturation regions of operation, and complementary feedback circuits connected to the power transistors and operating in conjunction with the resistors for biasing the helper transistors within the saturation regions of operation. Preferably, each of the power transistors are biased into the saturation regions by gate voltage swings of no more than 200 millivolts from the sub-threshold region.