Patents by Inventor Daniel Maynard

Daniel Maynard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10270567
    Abstract: An apparatus and method for operating an avionics data network includes a network switch core configured for a time-sensitive networking (TSN) schema, a set of TSN networking end nodes communicatively connected with the network switch core, a set of ARINC 664 part 7 (A664p7) networking end nodes communicatively connected with the network switch core, and an A664p7 legacy module connected with, or incorporated into, the network switch core and configured to receive a set of A664p7 networking data from the set of A664p7 networking end nodes.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: April 23, 2019
    Assignees: GE Aviation Systems Limited, GE Aviation Systems LLC
    Inventors: John Raymond Rang, Harry Molling, Daniel Maynard Berland, Timothy John Wood
  • Publication number: 20080104555
    Abstract: A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
    Type: Application
    Filed: November 29, 2007
    Publication date: May 1, 2008
    Inventors: David DeMaris, Timothy Dunham, William Leipold, Daniel Maynard, Michael Scaman, Shi Zhong
  • Publication number: 20080059929
    Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.
    Type: Application
    Filed: October 29, 2007
    Publication date: March 6, 2008
    Inventors: Evanthia Papadopoulou, Daniel Maynard
  • Publication number: 20070240090
    Abstract: Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands.
    Type: Application
    Filed: April 11, 2006
    Publication date: October 11, 2007
    Inventors: Jeanne Bickford, Markus Buehler, Jason Hibbeler, Juergen Koehl, Daniel Maynard
  • Publication number: 20070211933
    Abstract: Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region.
    Type: Application
    Filed: May 15, 2007
    Publication date: September 13, 2007
    Inventors: Bette Reuter, David DeMaris, Mark Lavin, William Leipold, Daniel Maynard, Maharaj Mukherjee
  • Publication number: 20070038970
    Abstract: A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
    Type: Application
    Filed: August 12, 2005
    Publication date: February 15, 2007
    Applicant: International Business Machines Corporation
    Inventors: David DeMaris, Timothy Dunham, William Leipold, Daniel Maynard, Michael Scaman, Shi Zhong
  • Publication number: 20060253806
    Abstract: A system, method and program product for predicting yield of a VLSI design. A method is providing including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.
    Type: Application
    Filed: May 9, 2005
    Publication date: November 9, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Allen, Daria Dooling, Jason Hibbeler, Daniel Maynard, Sarah Prue, Ralph Williams
  • Publication number: 20060023932
    Abstract: A system and method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.
    Type: Application
    Filed: July 27, 2004
    Publication date: February 2, 2006
    Applicant: International Business Machines Corporation
    Inventors: David DeMaris, Mark Lavin, William Leipold, Daniel Maynard, Maharaj Mukherjee
  • Publication number: 20050278663
    Abstract: A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated circuit for deviations from each design rule; (d) computing a score for each physical design rule, using the corresponding rule scoring equation assigned to each physical design rule, for which one or more deviations were found in step (c); and (e) computing a productivity score for the integrated circuit design based on the scores computed in step (d).
    Type: Application
    Filed: May 28, 2004
    Publication date: December 15, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas Kemerer, Daniel Maynard, Gustavo Tellez, Lijiang Wang, Peter Wissell
  • Publication number: 20050172247
    Abstract: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.
    Type: Application
    Filed: February 4, 2004
    Publication date: August 4, 2005
    Applicant: International Business Machines Corporation
    Inventors: Evanthia Papadopoulou, Daniel Maynard
  • Publication number: 20050094863
    Abstract: Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region.
    Type: Application
    Filed: October 30, 2003
    Publication date: May 5, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bette Bergman Reuter, David DeMaris, Mark Lavin, William Leipold, Daniel Maynard, Maharaj Mukherjee
  • Patent number: 5922737
    Abstract: The present invention relates to novel substituted N-methyl-N-(4-(4-(1H-benzimidazol-2-yl-amino)piperidin-1-yl)-2-(aryl)butyl )benzamide derivatives of the formula: ##STR1## stereoisomers thereof, and pharmaceutically acceptable salts thereof which are useful as histamine receptor antagonists and tachykinin receptor antagonists. Such antagonists are useful in the treatment of allergic rhinitis, including seasonal rhinitis and sinusitis; inflammatory bowel diseases, including Crohn's disease and ulcerative colitis; asthma; bronchitis; and emesis.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: July 13, 1999
    Assignee: Hoechst Marion Roussel, Inc.
    Inventors: George Daniel Maynard, John Michael Kane, Braulio Santiago, Elizabeth Mary Kudlacz, Larry Don Bratton, Christopher Robin Dalton