Patents by Inventor Daniel McKenna
Daniel McKenna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250230246Abstract: Provided herein are anti-MIC antibodies comprising one or more Fc domain mutations to eliminate Fc effector functions. Also provided herein are methods of use in treating cancer by administering the anti-MIC antibodies described herein.Type: ApplicationFiled: October 25, 2022Publication date: July 17, 2025Applicant: SAMYANG BIOPHARM USA INC.Inventor: Sean Daniel MCKENNA
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Publication number: 20240167714Abstract: Various examples described herein include various mechanisms, techniques, and methods to control atmospheric effects in a venue. For example, a method for controlling atmospheric effects in a venue is disclosed. The method includes querying and receiving a number of particulate sensors; analyzing particulate sensor-data received from the plurality of particulate sensors; making a determination whether the particulate sensor-data substantially agrees with a pre-determined target level of an environmental effect; and based on a determination that the particulate sensor-data does not agree substantially with the pre-determined target level of the environmental effect, sending a command signal to one or more haze generators to vary a haze production level; and based on a determination that the particulate sensor-data does agree substantially with the pre-determined target level of the environmental effect, making a determination whether additional haze sequences remain to be completed within the venue.Type: ApplicationFiled: November 20, 2023Publication date: May 23, 2024Inventors: John Daniel McKenna, Daniel Bernard McKenna
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Systems and methods for assigning domain identifiers to remote peripheral devices using a hypervisor
Patent number: 11755355Abstract: A processing system includes an interconnect, a master processing device including processing cores coupled to the interconnect, a hypervisor coupled to the interconnect and configured to allocate the processing cores to one or more virtual machines, domain configuration information including a domain identifier for each of the one or more virtual machines, remote peripheral devices coupled to the interconnect, and a domain access controller coupled to the interconnect and configured to receive the domain identifiers for the remote peripherals directly from the hypervisor through the interconnect.Type: GrantFiled: November 25, 2020Date of Patent: September 12, 2023Assignee: NXP USA, Inc.Inventors: David McDaid, Daniel McKenna, Steven Bruce McAslan -
Patent number: 11455026Abstract: A cascaded power system including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled and otherwise discharges the core voltage. The comparator circuitry monitors the voltage levels of the supply and core voltages and the control circuitry performs handshaking with the slave circuitry based partly on the voltages to ensure smooth transitioning between the normal and low power modes. The control circuitry asserts a low power good signal when the supply and core voltages are discharged, and de-asserts the low power good signal when the supply and core voltages are fully charged. A processor may rely on the low power mode signal for transitioning between power modes.Type: GrantFiled: August 21, 2020Date of Patent: September 27, 2022Assignee: NXP USA, Inc.Inventors: Loic Hureau, Jean-Philippe Meunier, Daniel McKenna
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SYSTEMS AND METHODS FOR ASSIGNING DOMAIN IDENTIFIERS TO REMOTE PERIPHERAL DEVICES USING A HYPERVISOR
Publication number: 20220164212Abstract: A processing system includes an interconnect, a master processing device including processing cores coupled to the interconnect, a hypervisor coupled to the interconnect and configured to allocate the processing cores to one or more virtual machines, domain configuration information including a domain identifier for each of the one or more virtual machines, remote peripheral devices coupled to the interconnect, and a domain access controller coupled to the interconnect and configured to receive the domain identifiers for the remote peripherals directly from the hypervisor through the interconnect.Type: ApplicationFiled: November 25, 2020Publication date: May 26, 2022Inventors: David McDaid, Daniel McKenna, Steven Bruce McAslan -
Patent number: 11175723Abstract: A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.Type: GrantFiled: April 20, 2020Date of Patent: November 16, 2021Assignee: NXP USA, Inc.Inventors: Loic Hureau, Daniel McKenna, Jean-Philippe Meunier, Thomas Henry Luedeke
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Publication number: 20210089114Abstract: A cascaded power system including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled and otherwise discharges the core voltage. The comparator circuitry monitors the voltage levels of the supply and core voltages and the control circuitry performs handshaking with the slave circuitry based partly on the voltages to ensure smooth transitioning between the normal and low power modes. The control circuitry asserts a low power good signal when the supply and core voltages are discharged, and de-asserts the low power good signal when the supply and core voltages are fully charged. A processor may rely on the low power mode signal for transitioning between power modes.Type: ApplicationFiled: August 21, 2020Publication date: March 25, 2021Inventors: Loic Hureau, Jean-Philippe Meunier, Daniel McKenna
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Patent number: 10860484Abstract: A data processor comprises a memory-management-unit for receiving external-operation-data from a CPU. The memory-management-unit sets a deterministic-quantity value for the external-operation-data based on the external-operation-data. The deterministic-quantity value may be either an active-value or an inactive-value. The data processor has a non-deterministic-processor-block for receiving a memory-signal from the memory-management-unit, and has a control-block configured to (i) send the memory-signal to an NDP-output-terminal if the deterministic-quantity value is the active-value, thereby bypassing a performance-enhancement-block, or (ii) send at least a portion of the memory-signal that is representative of the request for response-data to the performance-enhancement-block if the deterministic-quantity value is the inactive-value.Type: GrantFiled: April 7, 2017Date of Patent: December 8, 2020Assignee: NXP USA, Inc.Inventors: Daniel McKenna, Jeffrey Thomas Loeliger, Ewan Harwood
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Publication number: 20200371581Abstract: A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.Type: ApplicationFiled: April 20, 2020Publication date: November 26, 2020Inventors: Loic Hureau, Daniel McKenna, Jean-Philippe Meunier, Thomas Henry Luedeke
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Publication number: 20170344477Abstract: A data processor comprises a memory-management-unit for receiving external-operation-data from a CPU. The memory-management-unit sets a deterministic-quantity value for the external-operation-data based on the external-operation-data. The deterministic-quantity value may be either an active-value or an inactive-value. The data processor has a non-deterministic-processor-block for receiving a memory-signal from the memory-management-unit, and has a control-block configured to (i) send the memory-signal to an NDP-output-terminal if the deterministic-quantity value is the active-value, thereby bypassing a performance-enhancement-block, or (ii) send at least a portion of the memory-signal that is representative of the request for response-data to the performance-enhancement-block if the deterministic-quantity value is the inactive-value.Type: ApplicationFiled: April 7, 2017Publication date: November 30, 2017Inventors: Daniel MCKENNA, Jeffrey Thomas LOELIGER, Ewan HARWOOD
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Patent number: 9679541Abstract: A display system and a method of displaying an image are hereby presented. The display system is arranged to display an image on a screen which has at least one useful screen area which is intended to be seen by a user and at least one non-useful screen area which the user cannot see. The display device comprises a bandwidth saver unit arranged to determine a location on the screen of a current pixel to be displayed. If the pixel is located in a non-useful screen area of the screen, then the fetching from a data memory of a pixel value is inhibited by the bandwidth saver unit with respect to this pixel, and a replacement, fixed pixel value is passed to a data processing unit for further processing.Type: GrantFiled: May 8, 2015Date of Patent: June 13, 2017Assignee: NXP USA, Inc.Inventors: Vincent Aubineau, Daniel McKenna, Michael Andreas Staudenmaier
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Publication number: 20160163290Abstract: A display system and a method of displaying an image are hereby presented. The display system is arranged to display an image on a screen which has at least one useful screen area which is intended to be seen by a user and at least one non-useful screen area which the user cannot see. The display device comprises a bandwidth saver unit arranged to determine a location on the screen of a current pixel to be displayed. If the pixel is located in a non-useful screen area of the screen, then the fetching from a data memory of a pixel value is inhibited by the bandwidth saver unit with respect to this pixel, and a replacement, fixed pixel value is passed to a data processing unit for further processing.Type: ApplicationFiled: May 8, 2015Publication date: June 9, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: VINCENT AUBINEAU, DANIEL McKENNA, MICHAEL ANDREAS STAUDENMAIER
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Patent number: 7504937Abstract: The present self-configuring alarm network uses a decentralized (ad hoc or mesh) architecture that does not have a centralized “master” node. In this ad hoc network, any node is capable of behaving as if it were the “master node” by autonomously reporting the alarm event directly to all other nodes in the ad hoc network independent of where the alarm event occurred. The network of alarm devices, therefore, can spread the alarm indication to the entirety of the area covered by the network of alarm devices and can also differentiate between a general alarm indication and the locus of the alarm event.Type: GrantFiled: October 13, 2007Date of Patent: March 17, 2009Assignee: SelfLink LLCInventors: John Daniel McKenna, Daniel Bernard McKenna, James Michael Graziano
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Publication number: 20080030319Abstract: The present self-configuring emergency event alarm network uses a decentralized (ad hoc or mesh) architecture that does not have a centralized “master” node. In this ad hoc network, any node is capable of behaving as if it were the “master node” by autonomously reporting the alarm event directly to all other nodes in the ad hoc network independent of where the alarm event occurred. The network of alarm devices, therefore, can spread the alarm indication to the entirety of the area covered by the network of alarm devices and can also differentiate between a general alarm indication and the locus of the alarm event.Type: ApplicationFiled: October 13, 2007Publication date: February 7, 2008Applicant: Vulano Group, Inc.Inventors: John McKenna, Daniel McKenna, James Graziano
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Patent number: 7301455Abstract: The present self-configuring emergency event alarm network uses a decentralized (ad hoc or mesh) architecture that does not have a centralized “master” node. In this ad hoc network, any node is capable of behaving as if it were the “master node” by autonomously reporting the alarm event directly to all other nodes in the ad hoc network independent of where the alarm event occurred. The network of alarm devices, therefore, can spread the alarm indication to the entirety of the area covered by the network of alarm devices and can also differentiate between a general alarm indication and the locus of the alarm event.Type: GrantFiled: September 20, 2005Date of Patent: November 27, 2007Assignee: Vulano Group, Inc.Inventors: John Daniel McKenna, Daniel Bernard McKenna, James Michael Graziano
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Publication number: 20070063837Abstract: The present self-configuring emergency event alarm network uses a decentralized (ad hoc or mesh) architecture that does not have a centralized “master” node. In this ad hoc network, any node is capable of behaving as if it were the “master node” by autonomously reporting the alarm event directly to all other nodes in the ad hoc network independent of where the alarm event occurred. The network of alarm devices, therefore, can spread the alarm indication to the entirety of the area covered by the network of alarm devices and can also differentiate between a general alarm indication and the locus of the alarm event.Type: ApplicationFiled: September 20, 2005Publication date: March 22, 2007Applicant: Vulano Group, Inc.Inventors: John McKenna, Daniel McKenna, James Graziano
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Publication number: 20070021117Abstract: The present non-terrestrial feature transparency system spoofs the Air-to-Ground Network and the ground-based cellular communication network into thinking that the wireless subscriber devices have no special considerations associated with their operation, even though the wireless subscriber devices are located on an aircraft in flight. This architecture requires that the non-terrestrial feature transparency system on board the aircraft replicate the full functionality of a given wireless subscriber device, that has a certain predetermined feature set from a ground-based wireless service provider, at another wireless subscriber device located within the aircraft. This mirroring of wireless subscriber device attributes enables a localized cell for in-cabin communication yet retains the same wireless subscriber device attributes for the air-to-ground link.Type: ApplicationFiled: July 24, 2006Publication date: January 25, 2007Applicant: AirCell, Inc.Inventors: Daniel McKenna, Joseph Cruz, Kenneth Jochim, Anand Varadachari, Harold Saroka, Dandan Liu
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Publication number: 20060099981Abstract: An apparatus and method for providing a communique constituting program content concurrently delivered to a plurality of subscribers is described. Subscriber confirmation for each of a plurality of subscribers is stored. The subscribers whose wireless devices are active in a cell are identified. Data that identifies a plurality of subscribers is automatically generated. One or more cell are selected to provide communique to subscribers who are members of at least one community of subscribers and who are served by other cells of the cellular communication network. Data constituting said communique from a selected program source is routed, concurrently, to authorized wireless subscriber devices.Type: ApplicationFiled: September 19, 2005Publication date: May 11, 2006Inventors: Daniel McKenna, James Graziano
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Publication number: 20050277424Abstract: The wireless subscriber device that is operable in a communique system for cellular communication networks operates with existing cellular communication networks to provide communique communication services to subscribers. The Communique can be unidirectional (broadcast) or bidirectional (interactive) in nature and the extent of the Communique can be network-wide broadcast or narrowcast, where cells and/or cell sectors are grouped to cover a predetermined geographic area or demographic population or subscriber interest group to transmit information to subscribers who populate the target audience for the narrowcast transmissions.Type: ApplicationFiled: August 18, 2005Publication date: December 15, 2005Inventors: Daniel McKenna, James Graziano
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Publication number: 20050197134Abstract: The communique system for cellular communication networks operates with existing cellular communication networks to provide communique communication services to subscribers. The communique can be unidirectional (broadcast) or bidirectional (interactive) in nature and the extent of the communique can be network-wide broadcast or narrowcast, where one or more cells and/or cell sectors are grouped to cover a predetermined geographic area or demographic population or subscriber interest group to transmit information to subscribers who populate the target audience for the narrowcast transmissions. The communique system for cellular communication networks can dynamically allocate the available bandwidth to thereby serve subscribers with more control channel(s) and/or control channel bandwidth and/or communication channels and/or communication channels of greater bandwidth as the need presents itself.Type: ApplicationFiled: May 2, 2005Publication date: September 8, 2005Inventors: Daniel McKenna, James Graziano