Abstract: Methods and systems are described for monitoring and diagnosing the health of a processing unit within an embedded system using a power management integrated circuit (PMIC). The PMIC measures the current power consumption and temperature of the processing unit and compares these measurements against expected ranges derived from mission profiles, operational modes, and/or historical data. An alert is generated to prompt corrective action if the measurements are determined to be outside an expected range.

Abstract: A power management integrated circuit (PMIC) and method of operating a PMIC is described. The PMIC is configured to be coupled to a system on chip (SoC) including a number of power and clock domains. Each of the PMIC and the SoC have a shared key. The PMIC is configured to generate a challenge, output the challenge to the SoC and generate an expected-challenge-response determined from the challenge and the shared key. The PMIC is further configured to receive a challenge-response from the SoC and compare the challenge response with the expected-challenge-response. If the challenge response is different to the expected response, the PMIC may (i) apply a reset to the SoC, (ii) supply power to a subset of the SoC power domains and/or (iii) enable clocks of a subset of SoC clock domains.

Abstract: A processing system includes an interconnect, a master processing device including processing cores coupled to the interconnect, a hypervisor coupled to the interconnect and configured to allocate the processing cores to one or more virtual machines, domain configuration information including a domain identifier for each of the one or more virtual machines, remote peripheral devices coupled to the interconnect, and a domain access controller coupled to the interconnect and configured to receive the domain identifiers for the remote peripherals directly from the hypervisor through the interconnect.

Abstract: A cascaded power system including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled and otherwise discharges the core voltage. The comparator circuitry monitors the voltage levels of the supply and core voltages and the control circuitry performs handshaking with the slave circuitry based partly on the voltages to ensure smooth transitioning between the normal and low power modes. The control circuitry asserts a low power good signal when the supply and core voltages are discharged, and de-asserts the low power good signal when the supply and core voltages are fully charged. A processor may rely on the low power mode signal for transitioning between power modes.

Abstract: A processing system includes an interconnect, a master processing device including processing cores coupled to the interconnect, a hypervisor coupled to the interconnect and configured to allocate the processing cores to one or more virtual machines, domain configuration information including a domain identifier for each of the one or more virtual machines, remote peripheral devices coupled to the interconnect, and a domain access controller coupled to the interconnect and configured to receive the domain identifiers for the remote peripherals directly from the hypervisor through the interconnect.

Abstract: A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.

Abstract: A cascaded power system including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled and otherwise discharges the core voltage. The comparator circuitry monitors the voltage levels of the supply and core voltages and the control circuitry performs handshaking with the slave circuitry based partly on the voltages to ensure smooth transitioning between the normal and low power modes. The control circuitry asserts a low power good signal when the supply and core voltages are discharged, and de-asserts the low power good signal when the supply and core voltages are fully charged. A processor may rely on the low power mode signal for transitioning between power modes.

Abstract: A data processor comprises a memory-management-unit for receiving external-operation-data from a CPU. The memory-management-unit sets a deterministic-quantity value for the external-operation-data based on the external-operation-data. The deterministic-quantity value may be either an active-value or an inactive-value. The data processor has a non-deterministic-processor-block for receiving a memory-signal from the memory-management-unit, and has a control-block configured to (i) send the memory-signal to an NDP-output-terminal if the deterministic-quantity value is the active-value, thereby bypassing a performance-enhancement-block, or (ii) send at least a portion of the memory-signal that is representative of the request for response-data to the performance-enhancement-block if the deterministic-quantity value is the inactive-value.

Abstract: A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.

Abstract: A data processor comprises a memory-management-unit for receiving external-operation-data from a CPU. The memory-management-unit sets a deterministic-quantity value for the external-operation-data based on the external-operation-data. The deterministic-quantity value may be either an active-value or an inactive-value. The data processor has a non-deterministic-processor-block for receiving a memory-signal from the memory-management-unit, and has a control-block configured to (i) send the memory-signal to an NDP-output-terminal if the deterministic-quantity value is the active-value, thereby bypassing a performance-enhancement-block, or (ii) send at least a portion of the memory-signal that is representative of the request for response-data to the performance-enhancement-block if the deterministic-quantity value is the inactive-value.

Abstract: A display system and a method of displaying an image are hereby presented. The display system is arranged to display an image on a screen which has at least one useful screen area which is intended to be seen by a user and at least one non-useful screen area which the user cannot see. The display device comprises a bandwidth saver unit arranged to determine a location on the screen of a current pixel to be displayed. If the pixel is located in a non-useful screen area of the screen, then the fetching from a data memory of a pixel value is inhibited by the bandwidth saver unit with respect to this pixel, and a replacement, fixed pixel value is passed to a data processing unit for further processing.

Abstract: A display system and a method of displaying an image are hereby presented. The display system is arranged to display an image on a screen which has at least one useful screen area which is intended to be seen by a user and at least one non-useful screen area which the user cannot see. The display device comprises a bandwidth saver unit arranged to determine a location on the screen of a current pixel to be displayed. If the pixel is located in a non-useful screen area of the screen, then the fetching from a data memory of a pixel value is inhibited by the bandwidth saver unit with respect to this pixel, and a replacement, fixed pixel value is passed to a data processing unit for further processing.

Abstract: The present self-configuring emergency event alarm network uses a decentralized (ad hoc or mesh) architecture that does not have a centralized “master” node. In this ad hoc network, any node is capable of behaving as if it were the “master node” by autonomously reporting the alarm event directly to all other nodes in the ad hoc network independent of where the alarm event occurred. The network of alarm devices, therefore, can spread the alarm indication to the entirety of the area covered by the network of alarm devices and can also differentiate between a general alarm indication and the locus of the alarm event.

Abstract: The present self-configuring emergency event alarm network uses a decentralized (ad hoc or mesh) architecture that does not have a centralized “master” node. In this ad hoc network, any node is capable of behaving as if it were the “master node” by autonomously reporting the alarm event directly to all other nodes in the ad hoc network independent of where the alarm event occurred. The network of alarm devices, therefore, can spread the alarm indication to the entirety of the area covered by the network of alarm devices and can also differentiate between a general alarm indication and the locus of the alarm event.

Abstract: The present non-terrestrial feature transparency system spoofs the Air-to-Ground Network and the ground-based cellular communication network into thinking that the wireless subscriber devices have no special considerations associated with their operation, even though the wireless subscriber devices are located on an aircraft in flight. This architecture requires that the non-terrestrial feature transparency system on board the aircraft replicate the full functionality of a given wireless subscriber device, that has a certain predetermined feature set from a ground-based wireless service provider, at another wireless subscriber device located within the aircraft. This mirroring of wireless subscriber device attributes enables a localized cell for in-cabin communication yet retains the same wireless subscriber device attributes for the air-to-ground link.

Abstract: An apparatus and method for providing a communique constituting program content concurrently delivered to a plurality of subscribers is described. Subscriber confirmation for each of a plurality of subscribers is stored. The subscribers whose wireless devices are active in a cell are identified. Data that identifies a plurality of subscribers is automatically generated. One or more cell are selected to provide communique to subscribers who are members of at least one community of subscribers and who are served by other cells of the cellular communication network. Data constituting said communique from a selected program source is routed, concurrently, to authorized wireless subscriber devices.

Abstract: The wireless subscriber device that is operable in a communique system for cellular communication networks operates with existing cellular communication networks to provide communique communication services to subscribers. The Communique can be unidirectional (broadcast) or bidirectional (interactive) in nature and the extent of the Communique can be network-wide broadcast or narrowcast, where cells and/or cell sectors are grouped to cover a predetermined geographic area or demographic population or subscriber interest group to transmit information to subscribers who populate the target audience for the narrowcast transmissions.

Abstract: The communique system for cellular communication networks operates with existing cellular communication networks to provide communique communication services to subscribers. The communique can be unidirectional (broadcast) or bidirectional (interactive) in nature and the extent of the communique can be network-wide broadcast or narrowcast, where one or more cells and/or cell sectors are grouped to cover a predetermined geographic area or demographic population or subscriber interest group to transmit information to subscribers who populate the target audience for the narrowcast transmissions. The communique system for cellular communication networks can dynamically allocate the available bandwidth to thereby serve subscribers with more control channel(s) and/or control channel bandwidth and/or communication channels and/or communication channels of greater bandwidth as the need presents itself.

Abstract: A processor upgrade on a card suitable to be interconnected with an industry standard PCI bus.

Abstract: A controlled color light source including a lamp for projecting a beam of light, a power supply for energizing the lamp and a light conduit for sampling a portion of the light emitted from the lamp. A beam splitter is arranged to split the light from the conduit into two channels, and a pair of photo detectors, one for each channel are arranged to receive the light from the conduit via the beam splitter. A divider circuit has a pair of inputs and an output, the inputs being connected to the two photo detectors and an output circuit is connected to the output of the divider circuit for providing an output signal which is proportional to the color of light captured by the conduit.