Abstract: An ADC system may include an ADC, a comparator, a voltage source, a comparator output polarity control circuit and a comparator output counter. An analog input signal may be input to a first input of the comparator, and an output of the voltage source may be input to a second input of the comparator. The comparator may generate an output to the comparator output polarity control circuit, and the comparator output counter may count clock cycles while the comparator output is asserted and may assert a monitor output based on the comparator output counter value. The monitor output may be an interrupt, an alarm or other system alerts and may control system operation.

Abstract: A power monitor device includes a channel monitoring interface for monitoring a power rail, a data storage device including a data buffer, and measurement circuitry connected to the channel monitoring interface to generate a series of channel measurement samples associated with the power rail. The power monitor device includes control circuitry to store the channel measurement samples in the data buffer, detect a defined excursion event at an event detection time based at least on an event triggering sample of the channel measurement samples, and in response, store a sample set including the event triggering sample and at least one channel measurement sample stored in the data buffer prior to the event triggering sample. The control circuitry may subsequently receive a request for the stored sample set, and provide access to the stored sample set.

Abstract: An ADC system may include an ADC, a comparator, a voltage source, a comparator output polarity control circuit and a comparator output counter. An analog input signal may be input to a first input of the comparator, and an output of the voltage source may be input to a second input of the comparator. The comparator may generate an output to the comparator output polarity control circuit, and the comparator output counter may count clock cycles while the comparator output is asserted and may assert a monitor output based on the comparator output counter value. The monitor output may be an interrupt, an alarm or other system alerts and may control system operation.

Abstract: In an I2C communication system, dedicated address pins may enable a primary device to separately address multiple secondary devices. Upon a first transmission from the primary device, the logic level on each dedicated address pin may be saved in each secondary device. The address decoder circuit within each secondary device may use the saved address pin value for decoding transmissions from the primary device. The dedicated address pin may then be re-used for a separate function, as the logic level on the address pin has been saved.

Abstract: A switched-capacitor DC-DC converter circuit may convert an input voltage into a desired output voltage level. A comparator may compare a desired voltage level to a divided version of the output voltage. A fully digital control circuit comprising a frequency divider circuit, a counter circuit, a digital control logic circuit and a gain selection circuit may generate a gain value, and a phase generator may convert the gain value into clock phase signals and control settings to control a switch array to select capacitors to produce a desired output voltage.

Abstract: A system and method are disclosed wherein a risk score is generated by interrogating multiple sources of information across a network. The information is aggregated, such that every network action for individuals and organizations are turned into a unique behavioral model, which can be used as a unique identifier (“fingerprint”). This fingerprint is in turn used by a personalized Trust Guardian System to block, modify and/or allow network actions.

Abstract: A curvature compensated bandgap circuit that is capable of matching best-in-class two (2) parts-per-million performance without over-temperature trimming. This improves performance metrics for precision voltage reference products without requiring individual device tuning during production thereof. A core bandgap circuit comprises a main operational amplifier having a second order bowed voltage response over temperature. A ptat circuit is coupled to the core bandgap circuit to provide a sigmoidal third order shape for the bandgap voltage.

Abstract: A system and method are disclosed wherein a risk score is generated by interrogating multiple sources of information across a network. The information is aggregated, such that every network action for individuals and organizations are turned into a unique behavioral model, which can be used as a unique identifier (“fingerprint”). This fingerprint is in turn used by a personalized Trust Guardian System to block, modify and/or allow network actions.

Abstract: A system and method are disclosed wherein a risk score is generated by interrogating multiple sources of information across a network. The information is aggregated, such that every network action for individuals and organizations are turned into a unique behavioral model, which can be used as a unique identifier (“fingerprint”). This fingerprint is in turn used by a personalized Trust Guardian System to block, modify and/or allow network actions.

Abstract: A system and method are disclosed wherein a risk score is generated by interrogating multiple sources of information across a network. The information is aggregated, such that every network action for individuals and organizations are turned into a unique behavioral model, which can be used as a unique identifier (“fingerprint”). This fingerprint is in turn used by a personalized Trust Guardian System to block, modify and/or allow network actions.

Abstract: A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.

Abstract: An input circuit for an analog-to-digital converter (ADC) includes at least one bootstrap circuit, including at least one first switch for connecting electrical power to a first terminal of at least one capacitor; at least one second switch for connecting a second terminal of the at least one capacitor to a signal to be sampled; at least one third switch for connecting the first terminal of the at least one capacitor to the control gate of at least one sampling network input switch; at least one fourth switch for connecting the at least one sampling network input switch to a substrate; and at least one fifth switch for connecting the second terminal of the at least one capacitor to the substrate.

Abstract: A system including a sample-and-hold circuit for receiving a plurality of analog input signals; an analog-to-digital converter for converting each of the analog inputs to a digital signal; and a processor configured for implementing fractional delay recovery for the analog-to-digital converter. In some embodiments, the fractional delay recovery includes converting each of the plurality of analog input signals to a digital version in the predetermined order; upsampling each digital version in the predetermined order; digitally filtering each upsampled value in the predetermined order; and downsampling each filtered value in the predetermined order.

Abstract: A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.

Abstract: A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.

Abstract: An input circuit for an analog-to-digital converter (ADC) includes at least one bootstrap circuit, including at least one first switch for connecting electrical power to a first terminal of at least one capacitor; at least one second switch for connecting a second terminal of the at least one capacitor to a signal to be sampled; at least one third switch for connecting the first terminal of the at least one capacitor to the control gate of at least one sampling network input switch; at least one fourth switch for connecting the at least one sampling network input switch to a substrate; and at least one fifth switch for connecting the second terminal of the at least one capacitor to the substrate.

Abstract: A system including a sample-and-hold circuit for receiving a plurality of analog input signals; an analog-to-digital converter for converting each of the analog inputs to a digital signal; and a processor configured for implementing fractional delay recovery for the analog-to-digital converter. In some embodiments, the fractional delay recovery includes converting each of the plurality of analog input signals to a digital version in the predetermined order; upsampling each digital version in the predetermined order; digitally filtering each upsampled value in the predetermined order; and downsampling each filtered value in the predetermined order.

Abstract: A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.

Abstract: A versatile beach wrap, that closes securely allowing for garments to be removed and exchanged, the length of which can be adjusted, with a hood and fits into its own backpack for carrying.