Patents by Inventor Daniel Milon

Daniel Milon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5844139
    Abstract: A phased array sector scanning ultrasonic system includes a separate receive channel for each respective element in an ultrasonic transducer array. Each receive channel imparts a delay to the echo signal produced by each respective element. The delayed echo signals are summed to form a steered, dynamically focused and dynamically windowed receive beam even when the transmit beam does not emanate from the center of the array. The receiver has a beamformer including a multiplicity of beamformer channels. The beamformer dynamically increases delays to each channel without introducing unwanted discontinuities, by combining and synchronizing a FIFO and an interpolator. The interpolator uses "Wallace tree" adders to accumulate bit-shifted versions of the inputs. The number of additions is less than the number of bits which would be needed to represent equivalent coefficients.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: December 1, 1998
    Assignee: General Electric Company
    Inventors: Steven C. Miller, Gregory A. Lillegard, Daniel Milon
  • Patent number: 5797847
    Abstract: A phased array sector scanning ultrasonic system includes a separate beamformer channel for each respective element in an ultrasonic transducer array. Each beamformer channel has a three-stage complex FIR filter downstream of an analog-to-digital converter. Each filter circuit stage has a register pipeline, an in-phase FIR filter and a quadrature FIR filter. The first stage only has real samples, so there is a single pipeline. The other stages have complex inputs composed of in-phase (real) and quadrature (imaginary) samples, requiring a pipeline for each. Each register pipeline is made up of a multiplicity of registers connected in series. The number of registers in a given pipeline must equal the number of taps being used on the FIR filter immediately downstream of the register pipeline. The registers are clocked in synchronism and store successive echo data samples. Each register in the pipeline has an output connected to a respective tap of the corresponding FIR filter.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: August 25, 1998
    Assignee: General Electric Company
    Inventors: Steven C. Miller, Gregory A. Lillegard, Daniel Milon
  • Patent number: 5123084
    Abstract: The 3D display device of the invention is based on an octree structure of data pertaining to an object to be displayed. This structure is memorized in a memory associated with a cache memory sending blocks of data on a bus to which a geometrical processor and an image-generating circuit are connected. The geometrical processor generates the visible part of another octree corresponding to a target universe which may be positioned in any way in relation to the object universe (a cube enclosing all the data to be represented).
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: June 16, 1992
    Assignees: General Electric CGR S.A., Octree Corporation
    Inventors: Guy Prevost, Daniel Milon, Olivier Lis, Michel Delcroix, Bruce Edwards, Donald Meagher