Patents by Inventor Daniel Murray Jones

Daniel Murray Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11970161
    Abstract: A motion planner of an autonomous vehicle's computer system uses reconfigurable collision detection architecture hardware to perform a collision assessment on a planning graph for the vehicle prior to execution of a motion plan. For edges on the planning graph, which represent transitions in states of the vehicle, the system sets a probability of collision with a dynamic object in the environment based at least in part on the collision assessment. Depending on whether the goal of the vehicle is to avoid or collide with a particular dynamic object in the environment, the system then performs an optimization to identify a path in the resulting planning graph with either a relatively high or relatively low potential of a collision with the particular dynamic object. The system then causes the actuator system of the vehicle to implement a motion plan with the applicable identified path based at least in part on the optimization.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 30, 2024
    Assignees: DUKE UNIVERSITY, BROWN UNIVERSITY
    Inventors: Daniel Sorin, William Floyd-Jones, Sean Murray, George Konidaris, William Walker
  • Patent number: 11964393
    Abstract: A robot control system determines which of a number of discretizations to use to generate discretized representations of robot swept volumes and to generate discretized representations of the environment in which the robot will operate. Obstacle voxels (or boxes) representing the environment and obstacles therein are streamed into the processor and stored in on-chip environment memory. At runtime, the robot control system may dynamically switch between multiple motion planning graphs stored in off-chip or on-chip memory. The dynamically switching between multiple motion planning graphs at runtime enables the robot to perform motion planning at a relatively low cost as characteristics of the robot itself change. Various aspects of such robot motion planning are implemented in particular systems and methods that facilitate motion planning of the robot for various environments and tasks.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: April 23, 2024
    Assignee: REALTIME ROBOTICS, INC.
    Inventors: Daniel Sorin, George Konidaris, Sean Murray, William Floyd-Jones, Peter Howard, Xianchao Long
  • Patent number: 11939321
    Abstract: The invention provides a compound of formula (0): or a pharmaceutically acceptable salt, N-oxide or tautomer thereof; wherein: n is 1 or 2; X is CH or N; Y is selected from CH and C—F; Z is selected from C—Rz and N; R1 is selected from: -(Alk1)t-Cyc1; wherein t is 0 or 1; Optionally substituted C1-6 acyclic hydrocarbon groups R2 is selected from hydrogen; halogen; and C1-3 hydrocarbon groups optionally substituted with one or more fluorine atoms; R3 is hydrogen or a group L1-R7; R4 is selected from hydrogen; methoxy; and optionally substituted C1-3 alkyl; and R4a is selected from hydrogen and a C1-3 alkyl group; wherein Rz, Alk1, Cyc1, L1 and R7 are defined herein; provided that the compound is other than 6-benzyl-3-{2-[(2-methylpyrimidin-4-yl)amino]pyridin-4-yl}-7,8-dihydro-1,6-naphthyridin-5(6H)-one and 3-{2-[(2-methylpyrimidin-4-yl)amino]pyridin-4-yl}-7,8-dihydro-1,6-naphthyridin-5(6H)-one and salts and tautomers thereof.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: March 26, 2024
    Assignee: OTSUKA PHARMACEUTICAL CO., LTD.
    Inventors: Valerio Berdini, Ildiko Maria Buck, James Edward Harvey Day, Charlotte Mary Griffiths-Jones, Thomas Daniel Heightman, Steven Howard, Christopher William Murray, David Norton, Marc O'Reilly, Alison Jo-Anne Woolford, Michael Liam Cooke, David Cousin, Stuart Thomas Onions, Jonathan Martin Shannon, John Paul Watts
  • Patent number: 6081883
    Abstract: A scalable computer system has an interconnect bus providing communication links among a host processor and one or more function-specific processors, including a network processor (NP) and a file storage processor (FSP). The host processor provides a single interface to network administrators for maintaining the system. A bi-endian conversion system is provided to minimize a need for translating between big and little endian data types generated by diverse processors. The NP shares a single memory image with other processors and has a buffer memory for buffering requests from the network interfaces. The buffer memory has one or more segments which are dynamically allocatable to different processors. The FSP has a metadata cache for maintaining information on data being cached in the NP buffer memory. The FSP also has a write cache for buffering file write operations directed at disks.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: June 27, 2000
    Assignee: Auspex Systems, Incorporated
    Inventors: Paul Popelka, Tarun Kumar Tripathy, Richard Allen Walter, Paul Brian Del Fante, Murali Sundaramoorthy Repakula, Lakshman Narayanaswamy, Donald Wayne Sterk, Amod Prabhakar Bodas, Leslie Thomas McCutcheon, Daniel Murray Jones, Peter Kingsley Craft, Clive Mathew Philbrick, David Allan Higgen, Edward John Row