Patents by Inventor Daniel Musciano

Daniel Musciano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10608168
    Abstract: A planar Hall effect element be formed upon or can include a P-type substrate. The planar Hall effect element can also include a Hall plate region. The Hall plate region can include a first portion of an N-type layer disposed over the P-type substrate. The first portion of the N-type layer can include a top surface distal from the P-type substrate, and a continuous N-type outer boundary intersecting the top surface of the Hall plate region. The planar Hail effect element can also include an isolation region having a continuous outer boundary and having a continuous inner boundary, the continuous inner boundary in contact with all of the outer boundary of the Hall plate region, the P-type substrate and the first portion of the N-type layer not forming a P/N junction.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: March 31, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Juan Manuel Cesaretti, Gerardo A. Monreal, Daniel Musciano
  • Publication number: 20190103551
    Abstract: A planar Hall effect element be formed upon or can include a the P-type substrate. The planar Hall effect element can also include a Hall plate region. The Hall plate region can include a first portion of an N-type layer disposed over the P-type substrate. The first portion of the N-type layer can include a top surface distal from the P-type substrate, and a continuous N-type outer boundary intersecting the top surface of the Hall plate region. The planar Hall effect element can also include an isolation region having a continuous outer boundary and having a continuous inner boundary, the continuous inner boundary in contact with all of the outer boundary of the Hall plate region, the P-type substrate and the first portion of the N-type layer not forming a P/N junction.
    Type: Application
    Filed: October 4, 2017
    Publication date: April 4, 2019
    Applicant: Allegro MicroSystems, LLC
    Inventors: Juan Manuel Cesaretti, Gerardo A. Monreal, Daniel Musciano