Abstract: A disconnector device is connectable to pole-mounted equipment in a power grid. The disconnector device is activated in case of an overload condition, thereby disconnecting the pole-mounted equipment. The disconnector device comprises a passive radio device to be enabled via an incoming radio signal. The passive radio device, upon being enabled, transmits, in at least one state of the disconnector device, an indicator radio signal indicative of the respective state of the disconnector device, the state being one of an activated state and a deactivated state of the disconnector device.

Abstract: Disclosed is a leakage current measuring device for a grid protection system protecting a power distribution or transmission grid from damage in case of a power surge, the grid protection system including a disconnector device and a surge arrester connected in series along a grounding path, the grounding path connecting a phase of a power distribution or transmission grid through the surge arrester and the disconnector device to ground, the disconnector device being configured for being activated in case of an overload condition, thereby disconnecting the surge arrester. The leakage current measuring device includes a leakage current sensor for measuring a leakage current IL flowing along the grounding path, the leakage current IL being indicative of the electrical connection status of the disconnector device. The electrical connection status is one of an activated and an inactivated status of the disconnector device.

Abstract: A device, a method and a system for monitoring an electrical connection status of a disconnector device are disclosed. The disconnector device is connectable to pole-mounted equipment in a power distribution or transmission grid, thereby disconnecting the pole-mounted equipment. The connection status monitoring device includes a determining section configured to determine whether the disconnector device has been activated and to generate connection status indicator data, indicative of whether the disconnector device has been activated. The determining section further includes a wireless communication section which is adapted to connect to a wireless communication infrastructure using a wireless communication protocol, and to transmit the connection status indicator data over the wireless communication infrastructure.

Abstract: A monitoring system for remotely monitoring a state of pole-mounted equipment in a power distribution or transmission grid is provided. The pole-mounted equipment includes an indicator device configured to present state information indicative of a state of the pole-mounted equipment. The monitoring system includes a status monitoring device movable via a drive or propulsion system. The status monitoring device is configured to obtain the state information from the indicator device when located within a communication range of the indicator device.

Abstract: A device, a method and a system for monitoring an electrical connection status of a disconnector device (110). The disconnector device (110) being connectable to pole-mounted equipment in a power distribution or transmission grid (200), thereby disconnecting the pole-mounted equipment. The connection status monitoring device (100) comprises a determining section (130) configured to determine whether the disconnector device (110) has been activated and to generate connection status indicator data, indicative of whether the disconnector device (100, 110) has been activated. The determining section (130) further comprises a wireless communication section (140) which is adapted to connect to a wireless communication infrastructure (150) using a wireless communication protocol, and to transmit the connection status indicator data over the wireless communication infrastructure (150).

Abstract: A disconnector device is connectable to pole-mounted equipment in a power grid. The disconnector device is activated in case of an overload condition, thereby disconnecting the pole-mounted equipment. The disconnector device comprises a passive radio device to be enabled via an incoming radio signal. The passive radio device, upon being enabled, transmits, in at least one state of the disconnector device, an indicator radio signal indicative of the respective state of the disconnector device, the state being one of an activated state and a deactivated state of the disconnector device.

Abstract: Disclosed is a leakage current measuring device for a grid protection system protecting a power distribution or transmission grid from damage in case of a power surge, the grid protection system including a disconnector device and a surge arrester connected in series along a grounding path, the grounding path connecting a phase of a power distribution or transmission grid through the surge arrester and the disconnector device to ground, the disconnector device being configured for being activated in case of an overload condition, thereby disconnecting the surge arrester. The leakage current measuring device includes a leakage current sensor for measuring a leakage current IL flowing along the grounding path, the leakage current IL being indicative of the electrical connection status of the disconnector device. The electrical connection status is one of an activated and an inactivated status of the disconnector device.

Abstract: Exemplary embodiments are directed to a device with overvoltage protection that includes a varistor which can be connected by a first connection via a first line to high-voltage potential in a circuit arrangement, while a second connection is connected to ground via a second line. Furthermore, an additional impedance is provided, which can be connected between the second connection and ground or the first connection and the high voltage, or is mounted fixed in this position. The corresponding line can be interrupted by a switching arrangement. In order to test the withstand voltage of the circuit arrangement, at least one of the first and second line is interrupted and an additional impedance is inserted. A test voltage is applied to the circuit arrangement. After the overvoltage test, the interruption in at least one of the first and second lines is removed again.

Abstract: A surge arrester includes an active part, two electrodes resting against the active part and a connecting element. The active part and the electrodes are arranged in the connecting element. The connecting element is produced in an injection molding method or die-casting method, in which the connecting element shrinks during its production. As a result, the electrodes are firmly pressed against the active part.

Abstract: A surge arrester includes an active part, two electrodes resting against the active part and a connecting element. The active part and the electrodes are arranged in the connecting element. The connecting element is produced in an injection molding method or die-casting method, in which the connecting element shrinks during its production. As a result, the electrodes are firmly pressed against the active part.

Abstract: Exemplary embodiments are directed to a device with overvoltage protection that includes a varistor which can be connected by a first connection via a first line to high-voltage potential in a circuit arrangement, while a second connection is connected to ground via a second line. Furthermore, an additional impedance is provided, which can be connected between the second connection and ground or the first connection and the high voltage, or is mounted fixed in this position. The corresponding line can be interrupted by a switching arrangement. In order to test the withstand voltage of the circuit arrangement, at least one of the first and second line is interrupted and an additional impedance is inserted. A test voltage is applied to the circuit arrangement. After the overvoltage test, the interruption in at least one of the first and second lines is removed again.

Abstract: An apparatus and method are provided for updating one or more pluralities of pointers (i.e. one or more vector pointers) which are used for accessing one or more pluralities of data elements (i.e. one or more vector data elements) in a multi-ported memory. A first register file holds the vector pointers, a second register file holds stride data, and a plurality of functional units combine data from the second register file with data from the first register file. The results of combining the data are transferred to the first register file and represent updated vector pointers. Furthermore, a third register file is provided for holding modulus selector data to specify the size of a circular buffer for circular addressing.

Abstract: A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal processor (DSP) that is based on single-instruction-multiple-data (SIMD) principles and provides indirect access to vector elements. The disclosed configuration uses a processor with two vector units and associated registers, where the vector units are connected back to back for processing Viterbi decoder state metrics. Viterbi add instructions increment vectors of state metrics from a first register, performing a desired permutation of state metrics while reading them indirectly through vector pointers, and writing intermediate result vectors to a second register.

Abstract: A digital signal processor (DSP) includes a SIMD-based organization wherein operations are executed on a plurality of single-instruction multiple data (SIMD) datapaths or stages connected in cascade. The functionality and data values at each stage may be different, including a different width (e.g., a different number of bits per value) in each stage. The operands and destination for data in a computational datapath are selected indirectly through vector pointer registers in a vector pointers datapath. Each vector pointer register contains a plurality of pointers into a register file of a computational datapath.

Abstract: An apparatus and method are provided for updating one or more pluralities of pointers (i.e. one or more vector pointers) which are used for accessing one or more pluralities of data elements (i.e. one or more vector data elements) in a multi-ported memory. A first register file holds the vector pointers, a second register file holds stride data, and a plurality of functional units combine data from the second register file with data from the first register file. The results of combining the data are transferred to the first register file and represent updated vector pointers. Furthermore, a third register file is provided for holding modulus selector data to specify the size of a circular buffer for circular addressing.

Abstract: A digital signal processor (DSP) includes a SIMD-based organization wherein operations are executed on a plurality of single-instruction multiple data (SIMD) datapaths or stages connected in cascade. The functionality and data values at each stage may be different, including a different width (e.g., a different number of bits per value) in each stage. The operands and destination for data in a computational datapath are selected indirectly through vector pointer registers in a vector pointers datapath. Each vector pointer register contains a plurality of pointers into a register file of a computational datapath.

Abstract: A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal processor (DSP) that is based on single-instruction-multiple-data (SIMD) principles and provides indirect access to vector elements. The disclosed configuration uses a processor with two vector units and associated registers, where the vector units are connected back to back for processing Viterbi decoder state metrics. Viterbi add instructions increment vectors of state metrics from a first register, performing a desired permutation of state metrics while reading them indirectly through vector pointers, and writing intermediate result vectors to a second register.