Patents by Inventor Daniel Nelson Maynard

Daniel Nelson Maynard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and computer program product for semiconductor yield estimation
    Patent number: 8136066
    Abstract: A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: March 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeanne Paulette Spence Bickford, Jason D. Hibbeler, Juergen Koehl, William John Livingstone, Daniel Nelson Maynard
  • APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR YIELD ESTIMATION
    Publication number: 20090113364
    Abstract: A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.
    Type: Application
    Filed: December 1, 2008
    Publication date: April 30, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeanne Paulette Spence Bickford, Jason D. Hibbeler, Juergen Koehl, William John Livingstone, Daniel Nelson Maynard
  • Trench isolation for active areas and first level conductors
    Patent number: 6394638
    Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: May 28, 2002
    Assignee: International Business Machines Corporation
    Inventors: Edward W. Sengle, Mark D. Jaffe, Daniel Nelson Maynard, Mark Alan Lavin, Eric Jeffrey White, John A. Bracchitta
  • Formation of trench isolation for active areas and first level conductors
    Patent number: 6063687
    Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: May 16, 2000
    Assignee: International Business Machines Corporation
    Inventors: Edward W. Sengle, Mark D. Jaffe, Daniel Nelson Maynard, Mark Alan Lavin, Eric Jeffrey White, John A. Bracchitta
  • Trench isolation for active areas and first level conductors
    Patent number: 5734192
    Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: March 31, 1998
    Assignee: International Business Machines Corporation
    Inventors: Edward W. Sengle, Mark D. Jaffe, Daniel Nelson Maynard, Mark Alan Lavin, Eric Jeffrey White, John A. Bracchitta