Patents by Inventor Daniel Ortega

Daniel Ortega has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210254861
    Abstract: Solar receivers including a plurality of multi-scale solar absorbing surfaces arranged such that light or heat reflected from or emitted from one or more of the plurality of solar absorbing surfaces impinges one or more other solar absorbing surfaces of the solar receiver. The disclosed receivers increase the amount of absorbed energy from a concentrated light source, such as a heliostat field, and reduce radiative and convective heat losses.
    Type: Application
    Filed: February 2, 2021
    Publication date: August 19, 2021
    Inventors: Clifford K. Ho, Joshua Mark Christian, John Downing Pye, Jesus Daniel Ortega
  • Patent number: 10935281
    Abstract: Solar receivers including a plurality of multi-scale solar absorbing surfaces arranged such that light or heat reflected from or emitted from one or more of the plurality of solar absorbing surfaces impinges one or more other solar absorbing surfaces of the solar receiver. The disclosed receivers increase the amount of absorbed energy from a concentrated light source, such as a heliostat field, and reduce radiative and convective heat losses.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 2, 2021
    Assignees: National Technology & Engineering Solutions of Sandia, LLC, The Australian National University
    Inventors: Clifford K. Ho, Joshua Mark Christian, John Downing Pye, Jesus Daniel Ortega
  • Patent number: 10408259
    Abstract: A self-aligning roller bearing having inner and outer bearing ring elements and at least one row of roller elements disposed in between. The inner bearing ring element having a retaining flange provided on a first axial side of the roller bearing being configured for preventing the roller elements from falling out from the roller bearing. The roller bearing having a first sealing ring element located at the first axial side for sealing the first axial opening, the first sealing ring being rotatable in relation to the inner bearing ring and seals against a sealing mating surface of the inner bearing ring. The retaining flange has at least one filling slot configured for allowing the roller elements to be inserted in-between the inner and the outer bearing ring elements during assembly of the roller bearing, and the sealing mating surface being axially outside the at least one filling slot.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: September 10, 2019
    Assignee: AKTIEBOLAGET SKF
    Inventors: Erich Pfandl, Christian Cirar, Hakan Freden, Christian Kogler, Daniel Ortega
  • Patent number: 10252632
    Abstract: The present invention refers to a battery bank supply and replacement system in an electric vehicle, particularly for an electric vehicle used for the distribution of commercial goods. The system of the present invention comprises a battery bank mounted in a metal structure that is structurally coupled to a metal mounting structure arranged on the electric vehicle and a handling device consisting of a movable base. The movable base is aligned and secured to the metal mounting structure of the vehicle for removal of the battery bank from the vehicle towards the handling device or the other way round.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 9, 2019
    Assignee: GRUPO BIMBO, S.A.B. DE C.V.
    Inventors: Luis Angel Hernandez Lopez, Hugo Pichardo Anaya, Jose De Jesus Hernandez Jimenez, Leonardo Daniel Ortega Nolasco, Arturo Martinez Dorantes, Jorge Alejandro Garcia Mendez, Carlos Nava Ortiz
  • Publication number: 20190004916
    Abstract: A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 3, 2019
    Inventors: Raul Martinez, Enric Gibert Codina, Pedro Lopez, Marti Torrents Lapuerta, Polychronis Xekalakis, Georgios Tournavitis, Kyriakos A. Stavrou, Demos Pavlou, Daniel Ortega, Alejandro Martinez Vicente, Pedro Marcuello, Grigorios Magklis, Josep M. Codina, Crispin Gomez Requena, Antonio Gonzalez, Mirem Hyuseinova, Christos Kotselidis, Fernando Latorre, Marc Lupon, Carlos Madriles
  • Patent number: 10157063
    Abstract: A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Polychronis Xekalakis, Pedro Marcuello, Alejandro Vicente Martinez, Christos E. Kotselidis, Grigorios Magklis, Fernando Latorre, Raul Martinez, Josep M. Codina, Enric Gibert Codina, Crispin Gomez Requena, Antonio Gonzelez, Mirem Hyuseinova, Pedro Lopez, Marc Lupon, Carlos Madriles, Daniel Ortega, Demos Pavlou, Kyriakos A. Stavrou, Georgios Tournavitis
  • Publication number: 20180345805
    Abstract: The present invention refers to a battery bank supply and replacement system in an electric vehicle, particularly for an electric vehicle used for the distribution of commercial goods. The system of the present invention comprises a battery bank mounted in a metal structure that is structurally coupled to a metal mounting structure arranged on the electric vehicle and a handling device consisting of a movable base. The movable base is aligned and secured to the metal mounting structure of the vehicle for removal of the battery bank from the vehicle towards the handling device or the other way round.
    Type: Application
    Filed: September 21, 2016
    Publication date: December 6, 2018
    Inventors: Luis Angel HERNANDEZ LOPEZ, Hugo PICHARDO ANAYA, Jose De Jesus HERNANDEZ JIMENEZ, Leonardo Daniel ORTEGA NOLASCO, Arturo MARTINEZ DORANTES, Jorge Alejandro GARCIA MENDEZ, Carlos NAVA ORTIZ
  • Patent number: 10013326
    Abstract: A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Raul Martinez, Enric Gibert Codina, Pedro Lopez, Marti Torrents Lapuerta, Polychronis Xekalakis, Georgios Tournavitis, Kyriakos A. Stavrou, Demos Pavlou, Daniel Ortega, Alejandro Martinez Vicente, Pedro Marcuello, Grigorios Magklis, Josep M. Codina, Crispin Gomez Requena, Antonio Gonzalez, Mirem Hyuseinova, Christos Kotselidis, Fernando Latorre, Marc Lupon, Carlos Madriles
  • Patent number: 9811341
    Abstract: Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Kyriakos A. Stavrou, Enric Gibert Codina, Josep M. Codina, Crispin Gomez Requena, Antonio Gonzalez, Mirem Hyuseinova, Christos E. Kotselidis, Fernando Latorre, Pedro Lopez, Marc Lupon, Carlos Madriles Gimeno, Grigorios Magklis, Pedro Marcuello, Alejandro Martinez Vicente, Raul Martinez, Daniel Ortega, Demos Pavlou, Georgios Tournavitis, Polychronis Xekalakis
  • Patent number: 9374542
    Abstract: An image signal processor is described. The image signal processor includes a block checking circuit. The block checking circuit comprises comparison circuitry to compare a block of luminous pixel values against respective blocks of luminous pixel values that are processed by the image signal processor after the block of luminous pixel values. The block checking circuitry further comprises circuitry to record an entry in a table if one of the blocks of respective luminous pixel values match the block of luminous pixel values. The image signal processor is to store an image signal processing resultant of the block of luminous pixel values and present the stored resultant as a respective resultant for the one of the blocks of respective luminous pixel values if the one of the blocks of respective luminous pixel values matches the block of pixel values.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Kyriakos Stavrou, Pedro Marcuello, Grigorios Magklis, Javier Carretero Casado, Juan Fernandez, Carlos Madriles, Daniel Ortega, Demos Pavlou
  • Publication number: 20150281602
    Abstract: An image signal processor is described. The image signal processor includes a block checking circuit. The block checking circuit comprises comparison circuitry to compare a block of luminous pixel values against respective blocks of luminous pixel values that are processed by the image signal processor after the block of luminous pixel values. The block checking circuitry further comprises circuitry to record an entry in a table if one of the blocks of respective luminous pixel values match the block of luminous pixel values. The image signal processor is to store an image signal processing resultant of the block of luminous pixel values and present the stored resultant as a respective resultant for the one of the blocks of respective luminous pixel values if the one of the blocks of respective luminous pixel values matches the block of pixel values.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: KYRIAKOS STAVROU, PEDRO MARCUELLO, GRIGORIOS MAGKLIS, JAVIER CARRETERO CASADO, JUAN FERNANDEZ, CARLOS MADRILES, DANIEL ORTEGA, DEMOS PAVLOU
  • Patent number: 9145656
    Abstract: The present disclosure relates to a configurable seat assembly for a vehicle, a vehicle having a configurable seat assembly, and a method of reconfiguring a configurable seat assembly. The configurable seat assembly can be configured between two work configurations and includes a detachable seat panel that can be moved out of the way of an operator when the operator is reconfiguring the configurable seat assembly and moving between the two work configurations.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: September 29, 2015
    Assignee: DEERE & COMPANY
    Inventor: Daniel Ortega
  • Patent number: 9098581
    Abstract: Example methods for finding a text reading order in a document are described in which text zones are determined, the text zones are clustered using semantic measure and correlation and a reading order is found within each of the clusters.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: August 4, 2015
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Sherif Yacoub, Daniel Ortega, Paolo Faraboschi, Jose Abad Peiro
  • Publication number: 20150197919
    Abstract: The present disclosure relates to a configurable seat assembly for a vehicle, a vehicle having a configurable seat assembly, and a method of reconfiguring a configurable seat assembly. The configurable seat assembly can be configured between two work configurations and includes a detachable seat panel that can be moved out of the way of an operator when the operator is reconfiguring the configurable seat assembly and moving between the two work configurations.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicant: Deere & Company
    Inventor: Daniel Ortega
  • Patent number: 8948511
    Abstract: An automated document processing system is configured to normalize zones obtained from a document, and to extract articles from the normalized zones. In one configuration, the system receives at least one zone from the document, and applies at least one zone-breaking factor, thereby creating normalized sub-zones within which text lines are consistent with the at least one zone-breaking factor. The normalized sub-zones may be evaluated to obtain a reading order. Adjacent sub-zones are joined if text similarity exceeds a threshold value. Weakly joined sub-zones are separated where indicated by a topic vectors analysis of the weakly joined sub-zones.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: February 3, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Daniel Ortega, Sherif Yacoub, Jose Abad Peiro, Paolo Faraboschi
  • Patent number: 8928255
    Abstract: A dynamic step dimming interface is provided that allows a ballast to energize a lamp in a dim mode or a normal mode. The ballast includes a lamp controller that energizes the lamp using an oscillating current. The oscillating current is also provided to a voltage monitor, which indicates the voltage level of the oscillating current, and to a rectifier, which provides an output indicative of the oscillating current. The rectifier is responsive to user input indicating whether the dim mode or the normal mode is to be used. A processing circuit receives the voltage level from the voltage monitor and provides a mode command to the ballast, indicating the lamp mode, based on inputs received, and provides a reference voltage to a comparator. The comparator receives the rectifier output and the reference voltage, and generates a voltage indicative of a power level of the lamp for the processing circuit.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: January 6, 2015
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Arturo Hernandez Lopez, Markus Ziegler, Carlos Daniel Ortega Jaramillo
  • Publication number: 20140252970
    Abstract: A dynamic step dimming interface is provided that allows a ballast to energize a lamp in a dim mode or a normal mode. The ballast includes a lamp controller that energizes the lamp using an oscillating current. The oscillating current is also provided to a voltage monitor, which indicates the voltage level of the oscillating current, and to a rectifier, which provides an output indicative of the oscillating current. The rectifier is responsive to user input indicating whether the dim mode or the normal mode is to be used. A processing circuit receives the voltage level from the voltage monitor and provides a mode command to the ballast, indicating the lamp mode, based on inputs received, and provides a reference voltage to a comparator. The comparator receives the rectifier output and the reference voltage, and generates a voltage indicative of a power level of the lamp for the processing circuit.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 11, 2014
    Applicant: OSRAM SYLVANIA INC.
    Inventors: Arturo Hernandez Lopez, Markus Ziegler, Carlos Daniel Ortega Jaramillo
  • Publication number: 20140156976
    Abstract: Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 5, 2014
    Inventors: Enric Gibert Codina, Josep M. Codina, Fernando Latorre, Pedro Marcuello, Pedro Lopez, Crispin Gomez Requena, Antonio Gonzalez, Mirem Hyuseinova, Christos E. Kotselidis, Marc Lupon, Carlos Madriles Gimeno, Grigorios Magklis, Alejandro Martinez Vicente, Raul Martinez, Daniel Ortega, Demos Pavlou, Kyriakos A. Stavrou, Georgios Tournavitis, Polychronis Xekalakis
  • Publication number: 20140095849
    Abstract: A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Polychronis Xekalakis, Pedro Marcuello, Alejandro Vicente Martinez, Christos E. Kotselidis, Grigorios Magklis, Fernando Latorre, Raul Martinez, Josep M. Codina, Enric Gibert Codina, Crispin Gomez Requena, Antonio Gonzalez, Mirem Hyuseinova, Pedro Lopez, Marc Lupon, Carlos Madriles, Daniel Ortega, Demos Pavlou, Kyriakos A. Stavrou, Georgios Tournavitis
  • Publication number: 20140019721
    Abstract: Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: indentifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
    Type: Application
    Filed: December 29, 2011
    Publication date: January 16, 2014
    Inventors: Kyriakos A. Stavrou, Enric Gibert Codina, Josep M. Codina, Crispin Gomez Requena, Antonio Gonzalez, Mirem Hyuseinova, Christos E. Kotselidis, Fernando Latorre, Pedro Lopez, Marc Lupon, Carlos Madriles gimeno, Grigorios Magklis, Pedro Marcuello, Alejandro Martinez Vicente, Raul Martinez, Daniel Ortega, Demos Pavlou, Georgios Tournavitis, Polychronis Xekalakis