Patents by Inventor Daniel P. Daly
Daniel P. Daly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11750533Abstract: There is disclosed an example of a computing apparatus for providing a hardware-assisted virtual switch on a host, including: a hardware virtual switch (vSwitch) circuit; and a hardware virtual host (vHost) circuit, the vHost circuit having an interface driver specific to the hardware vSwitch and configured to provide a vHost data plane to: provide a plurality of hardware queues to communicatively couple the hardware vSwitch to a guest virtual function (VF); and present to a virtual network driver of the guest VF an interface that is backward compatible with a software network interface.Type: GrantFiled: October 24, 2017Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Daniel P. Daly, Cunming Liang, Jian Wang, Martin Roberts, Shih-Wei Chien, Gerald Alan Rogers
-
Publication number: 20230115114Abstract: There is disclosed an example of a computing apparatus for providing a hardware-assisted virtual switch on a host, including: a hardware virtual switch (vSwitch) circuit; and a hardware virtual host (vHost) circuit, the vHost circuit having an interface driver specific to the hardware vSwitch and configured to provide a vHost data plane to: provide a plurality of hardware queues to communicatively couple the hardware vSwitch to a guest virtual function (VF); and present to a virtual network driver of the guest VF an interface that is backward compatible with a software network interface.Type: ApplicationFiled: December 9, 2022Publication date: April 13, 2023Applicant: Intel CorporationInventors: Daniel P. Daly, Cunming Liang, Jian Wang, Martin Roberts, Shih-Wei Chien, Gerald Alan Rogers
-
Publication number: 20210141676Abstract: A network interface card (NIC) can be configured to monitor a first central processing unit (CPU) core mapped to a first receive queue having a receive queue length. The NIC can also be configured to determine whether the CPU core is overloaded based on the receive queue length. The NIC can also be configured to redirect data packets that were targeted from the first receive queue to the CPU core to another CPU core responsive to a determination that the CPU core is overloaded.Type: ApplicationFiled: January 19, 2021Publication date: May 13, 2021Inventors: Ren Wang, Daniel P. Daly, Antoine Kaufmann, Saikrishna Edupuganti, Tsung-Yuan C. Tai
-
Publication number: 20200403940Abstract: There is disclosed an example of a computing apparatus for providing a hardware-assisted virtual switch on a host, including: a hardware virtual switch (vSwitch) circuit; and a hardware virtual host (vHost) circuit, the vHost circuit having an interface driver specific to the hardware vSwitch and configured to provide a vHost data plane to: provide a plurality of hardware queues to communicatively couple the hardware vSwitch to a guest virtual function (VF); and present to a virtual network driver of the guest VF an interface that is backward compatible with a software network interface.Type: ApplicationFiled: October 24, 2017Publication date: December 24, 2020Applicant: Intel CorporationInventors: Daniel P. DALY, Cunming LIANG, Jian WANG, Martin ROBERTS, Shih-Wei CHIEN, Gerald Alan ROGERS
-
Patent number: 10268464Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.Type: GrantFiled: July 7, 2017Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte
-
Publication number: 20190012156Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.Type: ApplicationFiled: July 7, 2017Publication date: January 10, 2019Inventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte
-
Publication number: 20180285151Abstract: A network interface card (NIC) can be configured to monitor a first central processing unit (CPU) core mapped to a first receive queue having a receive queue length. The NIC can also be configured to determine whether the CPU core is overloaded based on the receive queue length. The NIC can also be configured to redirect data packets that were targeted from the first receive queue to the CPU core to another CPU core responsive to a determination that the CPU core is overloaded.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Ren Wang, Daniel P. Daly, Antoine Kaufmann, Saikrishna Edupuganti, Tsung-Yuan C. Tai
-
Patent number: 9904027Abstract: Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may comprise a plurality of sleds with individual sleds including one or more compute nodes; and a networking element coupled with a sled of the plurality of sleds and configured to communicatively connect the sled to one or more other components of the rack assembly via an optical communication system. The optical communication system may include an external optical cable configured to communicatively connect the networking element with the rack assembly. Other embodiments may be described and/or claimed.Type: GrantFiled: December 14, 2016Date of Patent: February 27, 2018Assignee: Intel CorporationInventors: Donald L. Faw, Uri V. Cummings, Terrence J. Trausch, Daniel P. Daly, Andrew C. Alduino
-
Patent number: 9898435Abstract: Apparatuses, methods and storage media associated with the exchange of messages between a hybrid switch and one or more baseboard management controllers (BMCs) are described herein. Specifically, an aggregate BMC controller (ABC) may be communicatively coupled with both the hybrid switch and the BMCs and configured to facilitate the exchange of messages between the hybrid switch and the one or more BMCs. Other embodiments may be described and/or claimed.Type: GrantFiled: December 10, 2014Date of Patent: February 20, 2018Assignee: Intel CorporationInventors: Patrick G. Kutch, Daniel P. Daly
-
Publication number: 20170126619Abstract: A first computational device receives a response generated by a second computational device for a third computational device. A target that is suitable for use by the third computational device is determined. The response is transmitted with an address of the target to the third computational device.Type: ApplicationFiled: January 12, 2017Publication date: May 4, 2017Inventors: Ramamurthy KRITHIVAS, Jacek RENIECKI, Daniel P. DALY, Madhusudhan RANGARAJAN
-
Publication number: 20170102510Abstract: Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may comprise a plurality of sleds with individual sleds including one or more compute nodes; and a networking element coupled with a sled of the plurality of sleds and configured to communicatively connect the sled to one or more other components of the rack assembly via an optical communication system. The optical communication system may include an external optical cable configured to communicatively connect the networking element with the rack assembly. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 14, 2016Publication date: April 13, 2017Inventors: Donald L. FAW, Uri V. CUMMINGS, Terrence J. TRAUSCH, Daniel P. DALY, Andrew C. ALDUINO
-
Patent number: 9609782Abstract: Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may comprise a plurality of sleds with individual sleds including one or more compute nodes; and a networking element coupled with a sled of the plurality of sleds and configured to communicatively connect the sled to one or more other components of the rack assembly via an optical communication system. The optical communication system may include an external optical cable configured to communicatively connect the networking element with the rack assembly. Other embodiments may be described and/or claimed.Type: GrantFiled: January 15, 2014Date of Patent: March 28, 2017Assignee: INTEL CORPORATIONInventors: Donald L. Faw, Uri V. Cummings, Terrence J. Trausch, Daniel P. Daly, Andrew C. Alduino
-
Patent number: 9577953Abstract: A first computational device receives a response generated by a second computational device for a third computational device. A target that is suitable for use by the third computational device is determined. The response is transmitted with an address of the target to the third computational device.Type: GrantFiled: September 27, 2013Date of Patent: February 21, 2017Assignee: INTEL CORPORATIONInventors: Ramamurthy Krithivas, Jacek Reniecki, Daniel P. Daly, Madhusudhan Rangarajan
-
Publication number: 20160170923Abstract: Apparatuses, methods and storage media associated with the exchange of messages between a hybrid switch and one or more baseboard management controllers (BMCs) are described herein. Specifically, an aggregate BMC controller (ABC) may be communicatively coupled with both the hybrid switch and the BMCs and configured to facilitate the exchange of messages between the hybrid switch and the one or more BMCs. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 10, 2014Publication date: June 16, 2016Inventors: Patrick G. Kutch, Daniel P. Daly
-
Publication number: 20150334867Abstract: Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may comprise a plurality of sleds with individual sleds including one or more compute nodes; and a networking element coupled with a sled of the plurality of sleds and configured to communicatively connect the sled to one or more other components of the rack assembly via an optical communication system. The optical communication system may include an external optical cable configured to communicatively connect the networking element with the rack assembly. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 15, 2014Publication date: November 19, 2015Inventors: Donald L. FAW, Uri V. CUMMINGS, Terrence J. TRAUSCH, Daniel P. DALY, Andrew C. ALDUINO
-
Publication number: 20150188731Abstract: One embodiment provides a computing device. The computing device includes a processor; a network interface comprising at least one port and a network interface identifier; and a distributed module configured to identify each directly connected other computing device, receive and store a forwarding policy from a centralized controller module, and forward a received packet based, at least in part, on the forwarding policy.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Inventor: Daniel P. Daly
-
Publication number: 20150095515Abstract: A first computational device receives a response generated by a second computational device for a third computational device. A target that is suitable for use by the third computational device is determined. The response is transmitted with an address of the target to the third computational device.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Inventors: Ramamurthy Krithivas, Jacek Reniecki, Daniel P. Daly, Madhusudhan Rangarajan