Abstract: The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide a signal and a plurality of parallel registers, wherein each of the parallel registers is adapted to access at least one of the plurality of serial registers at substantially the same time in response to detecting the signal.

Abstract: A method and apparatus for abandoning an interrupted task is provided. The method includes setting at least one of a plurality of logic elements associated with at least one of a plurality of first registers, wherein the plurality of first registers are adapted to access data stored in a plurality of second registers at substantially the same time when the plurality of logic elements are set. The method further includes resetting the plurality of logic elements substantially before the plurality of first registers access the data stored in the plurality of second registers.

Abstract: The present invention provides a method and apparatus for error recovery in a system. The apparatus comprises a directory cache adapted to store at least one entry and a control unit. The control unit is adapted to determine if at least one uncorrectable error exists in the directory cache and to place the directory cache offline in response to determining that the error is uncorrectable. The method comprises detecting an error in data stored in a storage device in the system, and determining if the detected error is correctable. The method further comprises making at least a portion of the storage device unavailable to one or more resources in the system in response to determining that the error is uncorrectable.

Abstract: A method and apparatus for reconfiguring a computing system on a system domain-by-system domain basis are disclosed. In one aspect of the present invention, the apparatus is a computing system comprises a plurality of system domains, a centerplane interconnecting the system domains, and a system controller. The system controller is capable of detecting a condition triggering a reconfiguration and reconfiguring a signal path affected by the condition from a first mode to a second mode.

Abstract: A method and apparatus for dynamically reconfiguring a computing system are disclosed. The method comprises detecting a predetermined condition triggering a reconfiguration of the computing system; and dynamically reconfiguring a signal path affected by the condition from a first mode to a second mode responsive to detecting the condition. The apparatus is a computing system, comprising: a plurality of I/O switches, a crossbar switch, a plurality of signal paths; and a system controller. Each signal path is defined by an I/O switch and the crossbar switch. The system controller is capable of detecting a predetermined condition triggering a reconfiguration and dynamically reconfiguring at least one of the signal paths affected by the condition from a first mode to a second mode.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Abstract: A method and apparatus for abandoning an interrupted task is provided. The method includes setting at least one of a plurality of logic elements associated with at least one of a plurality of first registers, wherein the plurality of first registers are adapted to access data stored in a plurality of second registers at substantially the same time when the plurality of logic elements are set. The method further includes resetting the plurality of logic elements substantially before the plurality of first registers access the data stored in the plurality of second registers.

Abstract: The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide a signal and a plurality of parallel registers, wherein each of the parallel registers is adapted to access at least one of the plurality of serial registers at substantially the same time in response to detecting the signal.

Abstract: A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested.

Abstract: A method and apparatus for reconfiguring a computing system on a system domain-by-system domain basis are disclosed. In one aspect of the present invention, the apparatus is a computing system comprises a plurality of system domains, a centerplane interconnecting the system domains, and a system controller. The system controller is capable of detecting a condition triggering a reconfiguration and reconfiguring a signal path affected by the condition from a first mode to a second mode.

Abstract: A method and apparatus for dynamically reconfiguring a computing system are disclosed. The method comprises detecting a predetermined condition triggering a reconfiguration of the computing system; and dynamically reconfiguring a signal path affected by the condition from a first mode to a second mode responsive to detecting the condition. The apparatus is a computing system, comprising: a plurality of I/O switches, a crossbar switch, a plurality of signal paths; and a system controller. Each signal path is defined by an I/O switch and the crossbar switch. The system controller is capable of detecting a predetermined condition triggering a reconfiguration and dynamically reconfiguring at least one of the signal paths affected by the condition from a first mode to a second mode.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Abstract: Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and hardware isolation from each other. Clusters can share dynamically definable ranges of memory with each other. The domain filter has software-loadable registers on the system units and in the global routers to set the parameters of the domains and clusters. The registers label individual inter-system transactions on the routers as invalid for system units not in the same domain or cluster as the originating unit.

Abstract: A device for attaching a host or network in data communications with a ring-topology network includes a plurality of contiguous stations which are independently attached in series to the ring-topology network. Each station has the ability to selectively receive data which is not received by the other stations in the device, and each station has the ability to coordinate its receipt of data with the other stations to insure that essentially all data is received by the device.

Abstract: Disclosed is a synchronous clock regenerator for generating a clock signal which can be reliably used to strobe a binary serial data signal. The incoming raw clock signal is fed into a tapped delay line which generates multiple delayed versions of the raw clock signal. Upon detection of a framing transition on the incoming data signal, the raw clock signal and multiple delayed clock signals are latched. The latched values are used to address a read only memory (ROM), the ROM containing codes specifying which, if any, of the set including the raw clock signal and multiple delayed clock signals provides the optimum phase to strobe the incoming data signal. The code read from the ROM is decoded, latched and fed to a l-of-n selector circuit.

Abstract: In a data processing system wherein a binary data message is protected by cyclic check codes, synchronization loss tolerance is incorporated by performing a binary transformation after encoding the message but prior to transmitting it or writing it to storage and by performing an inverse binary transformation upon receiving it or reading it from storage but prior to error checking. In one embodiment the transformation involves complementing a plurality of bits. In an alternate embodiment the transformation involves reversing the sequence of a plurality of contiguous bits.

Abstract: A device for use with a digital computer for storing standard software used by the computer and modifying the address portions of the standard software prior to transmission to the computer. The device includes a ROM package containing a ROM within which is stored a standard software subprogram written assuming it is stored at an absolute location in the computer's memory other than its actual location in the computer's memory system. Also included in the ROM package is a base register which can be loaded, under control of the operating system software, with an offset value reflecting the difference between the actual starting memory system location of the subprogram stored in the ROM and the assumed absolute starting location of the subprogram. Each ROM word includes an extra bit to indicate whether the corresponding data word contains an address requiring relocation. As a word is read out of ROM, a gating circuit tests whether an address relocation is required.

Abstract: A device for use with a digital computer for storing standard software used by the computer and modifying the address portions of the standard software prior to transmission to the computer. The device includes a ROM package containing a ROM within which is stored a standard software subprogram written assuming it is stored at an absolute location in the computer's memory other than its actual location in the computer's memory system. Also included in the ROM package is a base register which can be loaded, under control of the operating system software, with an offset value reflecting the difference between the actual starting memory system location of the subprogram stored in the ROM and the assumed absolute starting location of the subprogram. Each ROM word includes an extra bit to indicate whether the corresponding data word contains an address requiring relocation. As a word is read out of ROM, a gating circuit tests whether an address relocation is required.

Abstract: Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and hardware isolation from each other. Clusters can share dynamically definable ranges of memory with each other. The domain filter has software-loadable registers on the system units and in the global routers to set the parameters of the domains and clusters. The registers label individual inter-system transactions on the routers as invalid for system units not in the same domain or cluster as the originating unit.