Abstract: A multi-bank global memory system (GMS) for use with a multiprocessor computer system having a global bus. The GMS includes up to four global memory cards (GMCs) connected to the global bus. The GMCs are independently accessed. Each of the GMCs includes a common interface for buffering memory accesses and read reply data. Each of the GMCs also includes four memory banks. The common interface and memory banks are connected via a local bus. The memory banks are interleaved and are independently scheduled and accessed. The common interface and memory banks are each capable of performing posted write cycles and independently supplying read reply data subsequent to read requests. The common interface is capable of buffering, simultaneously, up to 8 writes per bank and 8 read replies per bank.