Abstract: A microcontroller provides a register change summary resource for summarizing register changes. Selected system registers within each resource are coupled to bits in resource change registers of the register change summary resource using logic that tracks accesses to the system registers. Each resource change register is coupled to a bit in a summary register. For systems with numerous system registers, each summary register may be coupled to a bit in a higher-level summary register. The register change summary resource further provides a software-controlled bit mask register. A change in a summary or resource change register may trigger a processor interrupt. Each register in the register change summary resource can be reset, also under software control. The registers within the register change summary resource are accessible through a dedicated software development port.

Abstract: An invalid configuration detection resource for identifying and reporting conflicts between system resources of a microcontroller or other device is provided. Selected system registers within each resource are monitored by discrete hardware logic within the invalid configuration detection resource. For each resource, a status register provides an encoding of the configuration for that resource. The invalid configuration detection resource then compares the status registers for invalid combinations, and encodes this information in a system status register. Alternatively, the invalid configuration detection resource monitors each selected system register, independent of the resource to which it belongs. Improper combinations of registers are then encoded in a system status register. An alternative embodiment uses software to replace the discrete hardware logic with a table that specifies invalid register combinations.

Abstract: A communication protocol is implemented by a control bus using multi-purpose bi-directional signal lines. The bi-directional signal lines provide a single control path shared among any number of system devices. Tokens, defined by the combination of states of the bi-directional signal lines, are transmitted over the control bus to other system devices. A token can represent a number of control commands. A received token is decoded by a system device using decode logic into an appropriate control command associated with the token according to a predefined logic table. Since a token can represent a control command only originated target devices or a control command only originated by initiator devices, the control bus can support both types of control commands with fewer pincount and point-to-point connections than conventional unidirectional control signalling.

Abstract: A debugging environment maintains object information (e.g., object size) concurrently with data optimization operations by a write buffer of a target system. Within the target system, a system bus is coupled between a system memory and a microcontroller. A data optimization operation by the write buffer is detected by monitoring of a merge signal of the system bus by a bus monitoring device. When a data optimization operation is detected, data optimization attributes (e.g., object information, data and address) associated with the data optimization operation are captured in the form of an object information signal responsive to a capture signal from the bus monitoring device. The data optimization attributes may be stored in either a trace cache of the target system or a memory of external trace capture equipment connected to the debug port, or a memory of the bus monitoring device.

Abstract: A direct memory access engine supports multiple virtual direct memory access channels. The direct memory access engine includes a direct memory access controller and a parameter table in memory containing parameters for a plurality of virtual direct memory access channels. The controller engine provides a single physical direct memory access channel and a plurality of virtual direct memory access channels. One direct memory access channel of the plurality of virtual direct memory access channels may be active at a given time. The parameters for the active channel may be loaded from the parameter table to a physical direct memory access control block and a physical direct memory access channel resource of the direct memory access controller. The physical direct memory access control block of the direct memory access controller utilizes the physical direct memory access channel resource to perform a direct memory access transfer for the active channel based on the loaded parameters.

Abstract: A processor-based device incorporating a software debug port that utilizes a JTAG or similar standardized interface, thereby providing a software debug communication mechanism that does not require a special bond-out package. In one embodiment of the invention, only standard JTAG pins are used for communications between a host platform and a target system incorporating a target processor. In another embodiment of the invention, the software debug port of the target processor is augmented for higher-speed access via optional sideband signals. When used in conjunction with an on-chip trace cache, the software debug port provides trace information for reconstructing instruction execution flow on the processor and is also capable of examining register contents without halting processor operation. The software debug port alleviates many of the packaging and clock synchronization problems confronting existing debug solutions.

Abstract: In-circuit emulation (ICE) and software debug facilities are included in a processor via a debug interface that interfaces a target processor to a host system. The debug interface includes a trace controller that monitors signals produced by the target processor to detect specified conditions and produce a trace record of the specified conditions including a notification of the conditions are selected information relating to the conditions. The trace controller formats a trace information record and stores the trace information record in a trace buffer in a plurality of trace data storage elements. The trace data storage elements have a format that includes a trace code (TCODE) field indicative of a type of trace information and a trace data (TDATA) field indicative of a type of trace information data.

Abstract: A trace analysis system for tracing the operation of a processor. The trace analysis system includes a process data module and a process instructions module. The process data module processes data accesses of selected test data. The process instruction module processes instruction execution of the selected test data based upon the detection of a non-sequential instruction having a target address. The process instructions module uses the target address of the non-sequential instruction to determine an instruction sequence.

Abstract: A debug interface supports data transfer using read and write system calls that communicate data without stopping an executing kernel. The printf( ) command passes an information string to an executing operating system. The information string summons the operating system to use a serial debug port to signal to a debug device, such as a host system, that is connected to the serial port. The debug interface-supported read and write operations and system calls allow the kernel and executing applications software, respectively, to continue executing during the read and write data transfers. The debug interface includes support for a plurality of extended function sideband signals that extend the functionality of the read and write functionality to allow the processor to concurrently run kernel and application programs while transferring data using read and write operation.

Abstract: To speed up interrupt processing by interrupt handlers executing with interrupts disabled, one or more processor registers in the computer system are reserved for exclusive use by software executing with interrupt disabled. Interrupt processing code can be written in a high level language. If the code generated by the high level language compiler uses non-reserved registers, these registers are saved by the interrupt handler in the reserved registers before the interrupt processing code is invoked. After execution of the interrupt processing code, the interrupt handler restores the non-reserved registers from the reserved registers. Saving the non-reserved registers in the reserved registers rather than in a memory improves the interrupt processing speed.