Abstract: A method, apparatus, and computer program product for implementing a high-performance data storage device using block-access memory devices are disclosed. According to an embodiment of the present invention, a storage device includes a block-access memory device configured to stored data in one or more physical sector addresses and a random-access memory device storing a logical-to-physical (L2P) sector address translation data structure. Also, the storage device includes a device manager, coupled to both the block-access memory device and the random-access memory. The device manager is configured to determine a physical sector address in the block-access memory device, in response to a data access request, wherein the data access request includes a logical sector address by mapping the logical sector address to a physical sector address using the L2P sector address translation data structure.

Abstract: A plurality of microphones are coupled in series to receive a bias current. A plurality of configurable switches may be used to select which ones of the microphones receive the bias current. The current source may be adjustable and the switches may be reconfigurable to dynamically change both the number of microphones being used and the amount of bias current being generated.

Abstract: In some embodiments, a method for testing a memory having a plurality of bits is provided and includes initializing each value in a first register to zero. Next, each value in a second register is initialized to one. Further, each bit in the memory is initialized to zero. A logical OR operation is applied to each bit in the memory with a bit value as the first operand and a corresponding register value in the first register as the second operand. Additionally, the method includes initializing each bit in the memory to one. Also, a logical AND operation is applied to each bit in the memory with the bit value as the first operand and a corresponding register value as the second operand.

Abstract: A method for use in a multifunction handheld device includes receiving a first plurality of digitally formatted files from a host device when coupled to the host device via a host interface. A selected one of the first plurality of digitally formatted files is played, the playing includes generating an audio output. The method monitors for a low voltage condition produced by a low battery voltage. When the low voltage condition is detected, a first fail safe algorithm is enabled to disable the audio output, store an audio setting corresponding to the playing of the audio output, and to shutdown the multifunction handheld device.

Abstract: A method for efficient battery use begins by monitoring at least one output of the handheld device for an overload condition. The processing continues by monitoring a system voltage produced by a DC-to-DC converter for a system low voltage condition. The process continues by monitoring voltage of the battery for a battery low voltage condition. The processing then continues by enabling one of a plurality of fail-safe algorithms based on when one or more of the overload condition, the system low voltage condition, and/or the battery low voltage condition are detected.

Abstract: A system and method for generating NTSC and PAL formatted composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components in accordance with NTSC and/or PAL formats. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Alternatively, a pixel clock frequency equal to an integer multiple of the carrier frequency may be used and modulation in accordance with the NTSC and PAL formats may be accomplished by inverting, setting to zero or leaving unmodified the chrominance components. The architecture of this system greatly reduces hardware complexity and bandwidth requirements.

Abstract: Aspects of the present invention provide a system for selectively processing a video signal in accordance with instructions from application software. The system contains a video decoder for converting an analog video signal to digital video data, and a controller for formatting and routing the digital video data. A list of control structures may be loaded into a memory associated with the controller. The control structures contain formatting and routing information used by the controller to process different portions of the video stream. The number and content of control structures as well as the correlation between the control structures and selected portions of the video stream may be flexibly determined by application software. In particular, the control structures may be configured such that certain portions of the video stream are routed to the CPU for processing, while other portions are routed to a display driver and output on a display device.

Abstract: A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Video control information is precalculated and stored in the display memory in advance. The digital composite video pixel data and video control information are then recovered from the display memory to produce a formatted stream of video data. The architecture of this system greatly reduces hardware complexity and bandwidth requirements. In addition, the process may be controlled by a media stream controller which is also adapted for audio and graphics processing.

Abstract: A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Video control information is precalculated and stored in the display memory in advance. The digital composite video pixel data and video control information are then recovered from the display memory to produce a formatted stream of video data. The architecture of this system greatly reduces hardware complexity and bandwidth requirements. In addition, the process may be controlled by a media stream controller which is also adapted for audio and graphics processing.