Abstract: Disclosed herein is a wearable drug delivery device including a container filled at least partially with a drug including at least one of a PCSK9 (Proprotein Convertase Subtilisin/Kexin Type 9) specific antibody, a granulocyte colony-stimulating factor (G-CSF), a sclerostin antibody, or a calcitonin gene-related peptide (CGRP) antibody. The wearable drug delivery device may include a needle and an insertion mechanism configured to insert the needle into a patient. A fluid pathway connector may define a sterile fluid flowpath between the container and the insertion mechanism. Optionally, a cannula initially disposed about the needle may be included. The cannula may be retained in the patient at an injection site created by the needle after the needle is withdrawn from the patient. Methods of assembly and operation are also provided.

Abstract: A process for increasing profits of a business engaged in the purchase of large numbers of products and/or products of volatile pricing from numerous vendors that operates to identify pricing errors, preferably typically before payment, by automatically reviewing all invoices typically in the order they are received to determine a best system price for each line item of each invoice by reference to pricing factors such as volume discount, seasonal pricing, price protection, commodity pricing, competition pricing, and cash discount recorded in memory for the subject item and reference to payment history data, accounts payable data and invoice data. From the pricing factors and associated data, a best system price is determined and compared to the invoice price for the item so that pricing errors are automatically uncovered and, if appropriate, flagged to identify the same as an exception for warning or notification.

Abstract: A process for increasing profits of a business engaged in the purchase of large numbers of products and/or products of volatile pricing from numerous vendors that operates to identify pricing errors, preferably typically before payment, by automatically reviewing all invoices typically in the order they are received to determine a best system price for each line item of each invoice by reference to pricing factors such as volume discount, seasonal pricing, price protection, commodity pricing, competition pricing, and cash discount recorded in memory for the subject item and reference to payment history data, accounts payable data and invoice data. From the pricing factors and associated data, a best system price is determined and compared to the invoice price for the item so that pricing errors are automatically uncovered and, if appropriate, flagged to identify the same as an exception for warning or notification.

Abstract: Disclosed is a method and structure for locally powering a semiconductor chip within a package. The structure and method incorporate a local voltage regulator mounted adjacent a semiconductor chip on a top surface of a carrier. The voltage regulator is electrically connected to a power plane disposed within the carrier. The voltage regulator continuously senses the reflected voltage of the power plane at a regulated output port and actively cancels time domain noise within its operational bandwidth. Mounting the voltage regulator on top of the carrier adjacent to the chip minimizes loop inductance between the regulator and power plane and also minimizes delay caused by impedance of the power plane on the current flowing to the chip.

Abstract: A multilayer ceramic semiconductor chip carrier is provided by a method of interconnecting ground, signal and power lines in a semiconductor chip carrier. The method involves forming a plurality of insulating layers with conductor lines comprising power and ground lines connected in parallel in a single plane formed in planes between the insulating layers. The parallel lines are directed in orthogonal directions in parallel between any two of the insulating layers with alternation successively between planes of X-directed lines and planes of Y-directed coplanar signal, power and ground lines. There are via connections formed between planes connecting a power line in one plane to another power line in another plane. Other via connections between planes connect a ground line in a first plane to another ground line in a second plane, and signal lines are formed in parallel between a ground line and a power line in a given plane.

Abstract: A multilayer ceramic semiconductor chip carrier is provided by a method of interconnecting ground, signal and power lines in a semiconductor chip carrier. The method involves forming a plurality of insulating layers with conductor lines comprising power and ground lines connected in parallel in a single plane formed in planes between the insulating layers. The parallel lines are directed in orthogonal directions in parallel between any two of the insulating layers with alternation successively between planes of X-directed lines and planes of Y-directed coplanar signal, power and ground lines. There are via connections formed between planes connecting a power line in one plane to another power line in another plane. Other via connections between planes connect a ground line in a first plane to another ground line in a second plane, and signal lines are formed in parallel between a ground line and a power line in a given plane.

Abstract: A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer.

Abstract: Disclosed is a multilayer ceramic substrate, and a method for forming same, which has an outer unsealed layer having a metallic via, an inner sealed layer having a composite via of metallic and ceramic materials and a further unsealed layer having a metallic via.

Abstract: A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer.

Abstract: A latch assembly for a closure, particularly a vehicle emergency exit window, comprising a pivotally mounted latch bar engageable with a cam or a pair of cams for providing the force which holds the closure against the structure surrounding the opening closed by the closure. In the preferred embodiment, both the latch bar and a pair of cams are pivotally mounted on the closure so that the cams are engageable with the structure. In other embodiments, the latch bar is pivotally mounted on the closure or on the structure and the cam or cams are either pivotally mounted or mounted in a fixed position on the structure.