Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

Abstract: A device structure includes a first interconnect layer, a second interconnect layer, a device layer including a comprising a plurality of devices, where the device layer is between the first interconnect layer and the second interconnect layer. The device structure further includes a dielectric layer adjacent the second interconnect layer, where the dielectric layer includes one or more of metallic dopants or a plurality of metal structures, wherein the plurality of metal structures is electrically isolated from interconnect structures but in contact with a dielectric material of the second interconnect layer, and where the individual ones of the plurality of metal structures is above a region including at least some of the plurality of devices. The device structure further includes a substrate adjacent to the dielectric layer and a heat sink coupled with the substrate.

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

Abstract: Embodiments of the present disclosure describe techniques for reducing in-plane distortion from wafer to wafer bonding using a dummy wafer. One embodiment is an apparatus formed using a dummy wafer, the apparatus comprising: a device layer fusion bonded to a first side of a carrier wafer, wherein the dummy wafer comprises a first wafer and the carrier wafer comprises a second wafer that is different than the first wafer; wherein the device layer comprise a portion of a third wafer that is different than the second wafer; and wherein a second opposite side of the carrier wafer includes: a removal process artifact, wherein a distortion signature present in the portion of the second wafer is indicative of the use of the dummy wafer fusion bonded to the second side of the carrier wafer, or a remainder of the dummy wafer. Other embodiments may be disclosed and/or claimed.

Abstract: Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.

Abstract: Techniques and mechanisms for bonding a first wafer to a second wafer in the presence of a fluid, the viscosity of which is greater than a viscosity of air at standard ambient temperature and pressure. In an embodiment, a first surface of the first wafer is brought into close proximity to a second surface of the second wafer. The fluid is provided between the first surface and the second surface when a first region of the first surface is made to contact a second region of the second surface to form a bond. The viscosity of the fluid mitigates a rate of propagation of the bond along a wafer surface, which in turn mitigates wafer deformation and/or stress between wafers. In another embodiment, the viscosity of the fluid is changed dynamically while the bond propagates between the first surface and the second surface.

Abstract: Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.

Abstract: Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.

Abstract: Techniques and mechanisms for forming a bond between wafers using a compliant layer. In an embodiment, a layer or layers of one or more compliant materials is provided on a first surface of a first wafer, and the one or more compliant layers are subsequently bonded to a second surface of a second wafer. The bonded wafers are heated to an elevated temperature at which a compliant layer exhibits non-elastic deformations to facilitate relaxation of stresses caused by wafer distortions. In another embodiment, a material of the compliant layer exhibits viscoelastic behavior at room temperature, wherein stress is mitigated by allowing wafer distortion to relax at room temperature.

Abstract: Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.

Abstract: Embodiments of the present disclosure describe techniques for reducing in-plane distortion from wafer to wafer bonding using a dummy wafer. One embodiment is an apparatus formed using a dummy wafer, the apparatus comprising: a device layer fusion bonded to a first side of a carrier wafer, wherein the dummy wafer comprises a first wafer and the carrier wafer comprises a second wafer that is different than the first wafer; wherein the device layer comprise a portion of a third wafer that is different than the second wafer; and wherein a second opposite side of the carrier wafer includes: a removal process artifact, wherein a distortion signature present in the portion of the second wafer is indicative of the use of the dummy wafer fusion bonded to the second side of the carrier wafer, or a remainder of the dummy wafer. Other embodiments may be disclosed and/or claimed.

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

Abstract: Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

Abstract: Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

Abstract: Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

Abstract: Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.

Abstract: Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

Abstract: A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.

Abstract: A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.