Patents by Inventor Daniel PEDONE

Daniel PEDONE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220148934
    Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.
    Type: Application
    Filed: October 14, 2021
    Publication date: May 12, 2022
    Applicant: Infineon Technologies AG
    Inventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Ralf Otremba, Daniel Pedone, Bernd Schmoelzer
  • Patent number: 11276680
    Abstract: A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: March 15, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Pedone, Hans-Joachim Schulze, Rolf Gerlach, Christian Kasztelan, Anton Mauder, Hubert Rothleitner, Wolfgang Scholz, Philipp Seng, Peter Tuerkes
  • Publication number: 20210305198
    Abstract: A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 30, 2021
    Inventors: Carsten von Koblinski, Daniel Pedone, Matteo Piccin, Roland Rupp, Chiew Li Tai, Jia Yi Wong
  • Publication number: 20210225795
    Abstract: A SiC power semiconductor device includes: a power semiconductor die including SiC and a metallization layer, wherein the metallization layer includes a first metal; a die carrier, wherein the power semiconductor die is arranged over the die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and a first intermetallic compound arranged between the power semiconductor die and the plating and including Ni3Sn4.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 22, 2021
    Inventors: Ralf Otremba, Gregor Langer, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Publication number: 20210134708
    Abstract: A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.
    Type: Application
    Filed: October 26, 2020
    Publication date: May 6, 2021
    Inventors: Ralf Otremba, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Patent number: 9825023
    Abstract: An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: November 21, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Basler, Erich Griebl, Joachim Mahler, Daniel Pedone, Wolfgang Scholz, Philipp Seng, Peter Tuerkes, Stephan Voss
  • Patent number: 9627335
    Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Stephan Henneck, Evelyn Napetschnig, Daniel Pedone, Bernhard Weidgans, Simon Faiss, Ivan Nikitin
  • Patent number: 9576944
    Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Christian Jaeger, Joachim Mahler, Daniel Pedone, Anton Prueckl, Hans-Joachim Schulze, Andre Schwagmann, Patrick Schwarz
  • Publication number: 20160163689
    Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 9, 2016
    Inventors: Johannes Georg Laven, Christian Jaeger, Joachim Mahler, Daniel Pedone, Anton Prueckl, Hans-Joachim Schulze, Andre Schwagmann, Patrick Schwarz
  • Publication number: 20160133620
    Abstract: A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.
    Type: Application
    Filed: October 22, 2015
    Publication date: May 12, 2016
    Inventors: Daniel Pedone, Hans-Joachim Schulze, Rolf Gerlach, Christian Kasztelan, Anton Mauder, Hubert Rothleitner, Wolfgang Scholz, Philipp Seng, Peter Tuerkes
  • Publication number: 20160111415
    Abstract: An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.
    Type: Application
    Filed: October 12, 2015
    Publication date: April 21, 2016
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Basler, Erich Griebl, Joachim Mahler, Daniel Pedone, Wolfgang Scholz, Philipp Seng, Peter Tuerkes, Stephan Voss
  • Publication number: 20150325535
    Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 12, 2015
    Applicant: Infineon Technologies AG
    Inventors: Stephan HENNECK, Evelyn NAPETSCHNIG, Daniel PEDONE, Bernhard WEIDGANS, Simon FAISS, Ivan NIKITIN