Abstract: The remotely accessible Integrated Debug Environment of this invention permits a user having only a computer and an Internet connection to remotely access an IDE configured for operating and debugging a selected target microprocessor or microcontroller. An IDE is set up, including a host computer which operates as a web server and as a target/debug controller. One or more target processors may be connected to the host computer, along with debug equipment, such as logic analyzers, ICE equipment, overlay memory, etc. The host computer includes toolsets that correspond to the available target processor(s). In order to execute or debug code on a selected target processor, a user connects to the host computer using a web browser, with which the user can determine the availability of target processors and other pertinent information.

Abstract: A processor-based device incorporating an on-chip instruction trace cache capable of providing information for reconstructing instruction execution flow. The trace information can be captured without halting normal processor operation. Both serial and parallel communication channels are provided for communicating the trace information to external devices. In the disclosed embodiment of the invention, instructions that disrupt the instruction flow are reported, particularly instructions in which the target address is in some way data dependent. For example, call instructions or unconditional branch instructions in which the target address is provided from a data register (or other memory location such as a stack) cause a trace cache entry to be generated. In the case of many unconditional branches or sequential instructions, no entry is placed into the trace cache because the target address can be completely determined from the instruction stream.

Abstract: A processor-based device incorporating an on-chip trace cache and supporting circuitry for providing software performance profiling information. A trigger control register is configured to initialize and trigger (start) a first on-chip counter upon entry into a selected procedure. A second trigger control register is used to stop the first counter when the procedure prologue of the selected procedure is entered. Counter values reflecting the lapsed execution time of the selected procedure are then stored in the on-chip trace cache. Similar techniques can be used to measure other parameters such as interrupt handler execution times. In the disclosed embodiment of the invention, a second counter is also provided. The second counter runs continually, but is reset to zero following a stop trigger event caused by the second trigger control register. The stop trigger event also causes the value of the second counter to be placed in the on-chip trace cache.