Patents by Inventor Daniel Pham
Daniel Pham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240081829Abstract: A system for delivering an implant device to a vascular site in a patient a delivery pusher apparatus, an implant device detachably connected to the delivery pusher apparatus by a tether having a distal end connected to a proximal end of the implant device, wherein the tether is substantially non-tensioned when connecting the implant device to the delivery pusher, and an electrical heating element configured coaxially around at least a portion of the tether, wherein heat generated by the heating element severs the tether at a point near the proximal end of the implant device.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Applicant: MicroVention, Inc.Inventors: Claudio Plaza, Scott Hemmelgarn, Eileen Charlton, Todd Hewitt, Philippe Marchand, Daniel Welsh, William R. Patterson, Son Pham
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Patent number: 9419137Abstract: A method of straining fins of a FinFET device by using a stress memorization film and the resulting device are provided. Embodiments include providing a plurality of bulk Si fins, the plurality of bulk Si fins having a recessed oxide layer therebetween; forming a stress memorization layer over the plurality of bulk Si fins and the recessed oxide layer; annealing the stress memorization layer, the plurality of bulk Si fins, and the recessed oxide layer; and removing the stress memorization layer.Type: GrantFiled: March 9, 2015Date of Patent: August 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Abner Bello, Xiuyu Cai, Hugh Porter, Daniel Pham
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Patent number: 9263537Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.Type: GrantFiled: October 28, 2014Date of Patent: February 16, 2016Assignees: GLOBALFOUNDRIES Inc., International Business Machines CorporationInventors: Daniel Pham, Xiuyu Cai, Balasubramanian Pranatharthiharan, Pranita Kulkarni
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Patent number: 9219002Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.Type: GrantFiled: September 17, 2013Date of Patent: December 22, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Zhenyu Hu, Andy Wei, Qi Zhang, Richard J. Carter, Hongliang Shen, Daniel Pham, Sruthi Muralidharan
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Patent number: 9064801Abstract: A method of forming a semiconductor structure includes forming a metal gate above a semiconductor substrate and gate spacers adjacent to the metal gate surrounded by an interlevel dielectric (ILD) layer. The gate spacers and the metal gate are recessed until a height of the metal gate is less than a height of the gate spacers. An etch stop liner is deposited above the gate spacers and the metal gate. A gate cap is deposited above the etch stop liner to form a bi-layer gate cap. A contact hole is formed in the ILD layer adjacent to the metal gate, the etch stop liner in the bi-layer gate cap prevents damage of the gate spacers during formation of the contact hole. A conductive material is deposited in the contact hole to form a contact to a source-drain region in the semiconductor substrate.Type: GrantFiled: January 23, 2014Date of Patent: June 23, 2015Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., SAMSUNG ELECTRONICS CO., LTD.Inventors: David V. Horak, Jin Wook Lee, Daniel Pham, Shom S. Ponoth, Balasubramanian Pranatharthiharan
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Publication number: 20150076653Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.Type: ApplicationFiled: September 17, 2013Publication date: March 19, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Zhenyu Hu, Andy Wei, Qi Zhang, Richard J. Carter, Hongliang Shen, Daniel Pham, Sruthi Muralidharan
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Publication number: 20150050792Abstract: Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench.Type: ApplicationFiled: August 13, 2013Publication date: February 19, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Srikanth B. Samavedam, Zhenyu Hu, Andy Wei, Qi Zhang, Nicholas V. LiCausi, Daniel Pham
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Publication number: 20150041869Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: Daniel Pham, Xiuyu Cai, Balasubramanian Pranatharthiharan, Pranita Kulkarni
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Publication number: 20150001628Abstract: An improved structure and method for forming isolation between two adjacent field effect transistors is disclosed. A large substrate cavity is formed between gates of the two adjacent transistors. The substrate cavity is filled with an epitaxial material such as epitaxial silicon, silicon germanium, or III-V compound semiconductor to form an epitaxial region. A cavity is then formed in the epitaxial material, dividing the epitaxial region into two epitaxial regions that serve as source-drain regions.Type: ApplicationFiled: June 27, 2013Publication date: January 1, 2015Inventors: Nicholas V. LiCausi, Daniel Pham, Andy Chi-Hung Wei, Zhenyu Hu
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Patent number: 8906754Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.Type: GrantFiled: March 15, 2013Date of Patent: December 9, 2014Assignees: GLOBALFOUNDRIES Inc., International Business Machines CorporationInventors: Daniel Pham, Xiuyu Cai, Balasubramanian Pranatharthiharan, Pranita Kulkarni
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Patent number: 8871582Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.Type: GrantFiled: March 15, 2013Date of Patent: October 28, 2014Assignees: GLOBALFOUNDRIES Inc., International Business Machines CorporationInventors: Daniel Pham, Xiuyu Cai, Balasubramanian Pranatharthiharan, Pranita Kulkarni
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Patent number: 8846491Abstract: Embodiments herein provide approaches for forming a diffusion break during a replacement metal gate process. Specifically, a semiconductor device is provided with a set of replacement metal gate (RMG) structures over a set of fins patterned from a substrate; a dielectric material over an epitaxial junction area; an opening formed between the set of RMG structures and through the set of fins, wherein the opening extends through the dielectric material, the expitaxial junction area, and into the substrate; and silicon nitride (SiN) deposited within the opening to form the diffusion break.Type: GrantFiled: June 19, 2013Date of Patent: September 30, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel Pham, Zhenyu Hu, Andy Wei, Nicholas V. LiCausi
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Publication number: 20140264487Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicants: International Business Machines Corporation, GLOBALFOUNDRIES Inc.Inventors: Daniel Pham, Xiuyu Cai, Balasubramanian Pranatharthiharan, Pranita Kulkarni
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Publication number: 20140264486Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Daniel Pham, Xiuyu Cai, Balasubramanian Pranatharthiharan, Pranita Kulkarni
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Publication number: 20110195556Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.Type: ApplicationFiled: April 15, 2011Publication date: August 11, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Daniel PHAM, Bich-Yen NGUYEN
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Patent number: 7943988Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.Type: GrantFiled: September 5, 2008Date of Patent: May 17, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Daniel Pham, Bich-Yen Nguyen
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Publication number: 20100059817Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.Type: ApplicationFiled: September 5, 2008Publication date: March 11, 2010Inventors: DANIEL PHAM, Bich-Yen Nguyen
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Publication number: 20020094684Abstract: A method and apparatus for cleaning semiconductor wafers during the fabrication process. In the method, a foam is passed over the wafer surfaces in order to remove particulate matter. Viscosity, electrical charge and recipe of the foam may be varied to enhance wafer cleaning. In a preferred embodiment of the present invention, a number of wafers are situated vertically in a cleaning chamber and allowed to rotate between a number of axially rotatable rollers, with at least one roller also being a drive roller, while foam is passed across the wafer surfaces.Type: ApplicationFiled: November 27, 2001Publication date: July 18, 2002Inventors: George J. Hirasaki, Daniel Pham