Abstract: Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a semiconductor layer, a source region and a drain region disposed in the semiconductor layer, a gate electrode over the semiconductor layer between the source region and the drain region, and a gate dielectric layer between the gate electrode and the semiconductor layer. The semiconductor device also includes an insulating layer disposed between a portion of the gate electrode and the gate dielectric layer, and a spacer disposed between a sidewall of the insulating layer and the gate electrode.

Abstract: Disclosed herein is a method including receiving a semiconductor substrate having a first semiconductor material layer and a different second semiconductor material layer disposed on the first semiconductor material layer, forming a drift region overlapping the first semiconductor material layer, the drift region doped to a first conductivity type, forming a gate electrode layer over the field relief insulator, removing a first portion of the second semiconductor material layer to form a trench that exposes a first portion of the first semiconductor material layer, removing the exposed first portion of the first semiconductor material layer to extend the trench under the gate electrode layer toward the drift region, wherein a second portion of the second semiconductor material layer is exposed in the extended trench, and forming a dielectric isolation structure in the extended trench, the dielectric isolation structure touching the second portion of the second semiconductor material layer.

Abstract: Disclosed examples include microelectronic devices, e.g. Integrated circuits. One example includes a microelectronic device including a nanosheet lateral drain extended metal oxide semiconductor (LDMOS) transistor with source and drain regions having a first conductivity type extending into a semiconductor substrate having an opposite second conductivity type. A superlattice of alternating layers of nanosheets of a channel region and layers of gate conductor are separated by a gate dielectric, the superlattice extending between the source region and the drain region. A drain drift region of the first conductivity type extends under the drain region and a body region of the second type extends around the source region.

Abstract: A method of straining fins of a FinFET device by using a stress memorization film and the resulting device are provided. Embodiments include providing a plurality of bulk Si fins, the plurality of bulk Si fins having a recessed oxide layer therebetween; forming a stress memorization layer over the plurality of bulk Si fins and the recessed oxide layer; annealing the stress memorization layer, the plurality of bulk Si fins, and the recessed oxide layer; and removing the stress memorization layer.

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Abstract: A method of forming a semiconductor structure includes forming a metal gate above a semiconductor substrate and gate spacers adjacent to the metal gate surrounded by an interlevel dielectric (ILD) layer. The gate spacers and the metal gate are recessed until a height of the metal gate is less than a height of the gate spacers. An etch stop liner is deposited above the gate spacers and the metal gate. A gate cap is deposited above the etch stop liner to form a bi-layer gate cap. A contact hole is formed in the ILD layer adjacent to the metal gate, the etch stop liner in the bi-layer gate cap prevents damage of the gate spacers during formation of the contact hole. A conductive material is deposited in the contact hole to form a contact to a source-drain region in the semiconductor substrate.

Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Abstract: Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench.

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract: An improved structure and method for forming isolation between two adjacent field effect transistors is disclosed. A large substrate cavity is formed between gates of the two adjacent transistors. The substrate cavity is filled with an epitaxial material such as epitaxial silicon, silicon germanium, or III-V compound semiconductor to form an epitaxial region. A cavity is then formed in the epitaxial material, dividing the epitaxial region into two epitaxial regions that serve as source-drain regions.

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.

Abstract: Embodiments herein provide approaches for forming a diffusion break during a replacement metal gate process. Specifically, a semiconductor device is provided with a set of replacement metal gate (RMG) structures over a set of fins patterned from a substrate; a dielectric material over an epitaxial junction area; an opening formed between the set of RMG structures and through the set of fins, wherein the opening extends through the dielectric material, the expitaxial junction area, and into the substrate; and silicon nitride (SiN) deposited within the opening to form the diffusion break.

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

Abstract: A method and apparatus for cleaning semiconductor wafers during the fabrication process. In the method, a foam is passed over the wafer surfaces in order to remove particulate matter. Viscosity, electrical charge and recipe of the foam may be varied to enhance wafer cleaning. In a preferred embodiment of the present invention, a number of wafers are situated vertically in a cleaning chamber and allowed to rotate between a number of axially rotatable rollers, with at least one roller also being a drive roller, while foam is passed across the wafer surfaces.