Patents by Inventor Daniel PIEBER

Daniel PIEBER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of processing a semiconductor wafer, semiconductor wafer, and semiconductor die produced from a semiconductor wafer
    Patent number: 11610817
    Abstract: A method of processing a semiconductor wafer includes: forming a first metal layer or metal layer stack on a backside of the semiconductor wafer; forming a plating preventative layer on the first metal layer or metal layer stack, the plating preventative layer being formed at least over a kerf region of the semiconductor wafer and such that part of the first metal layer or metal layer stack is uncovered by the plating preventative layer, wherein the kerf region defines an area for dividing the semiconductor wafer along the kerf region into individual semiconductor dies; and plating a second metal layer or metal layer stack on the part of the first metal layer or metal layer stack uncovered by the plating preventative layer, wherein the plating preventative layer prevents plating of the second metal layer or metal layer stack over the kerf region.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: March 21, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Kitzler, John Cooper, Jakob Simon Dohr, Michael Knabl, Matic Krivec, Daniel Pieber
  • METHOD OF PROCESSING A SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DIE PRODUCED FROM A SEMICONDUCTOR WAFER
    Publication number: 20220301933
    Abstract: A method of processing a semiconductor wafer includes: forming a first metal layer or metal layer stack on a backside of the semiconductor wafer; forming a plating preventative layer on the first metal layer or metal layer stack, the plating preventative layer being formed at least over a kerf region of the semiconductor wafer and such that part of the first metal layer or metal layer stack is uncovered by the plating preventative layer, wherein the kerf region defines an area for dividing the semiconductor wafer along the kerf region into individual semiconductor dies; and plating a second metal layer or metal layer stack on the part of the first metal layer or metal layer stack uncovered by the plating preventative layer, wherein the plating preventative layer prevents plating of the second metal layer or metal layer stack over the kerf region.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventors: Andreas Kitzler, John Cooper, Jakob Simon Dohr, Michael Knabl, Matic Krivec, Daniel Pieber
  • METHOD WITH MECHANICAL DICING PROCESS FOR PRODUCING MEMS COMPONENTS
    Publication number: 20210253421
    Abstract: A method for producing MEMS components comprises generating a carrier having a plurality of recesses. An adhesive structure is arranged on the carrier and in the recesses. A semiconductor wafer is generated, which has a plurality of MEMS structures arranged at the first main surface of the semiconductor wafer. The adhesive structure is attached to the first main surface of the semiconductor wafer, with the recesses being arranged above the MEMS structures and the adhesive structure not contacting the MEMS structures. The semiconductor wafer is singulated into a plurality of MEMS components by applying a mechanical dicing process.
    Type: Application
    Filed: February 8, 2021
    Publication date: August 19, 2021
    Inventors: Andre BROCKMEIER, Markus BERGMEISTER, Bernhard GOLLER, Daniel PIEBER, Sokratis SGOURIDIS