Abstract: In one or more implementations, a semiconductor device can include a first compound semiconductor device coupled to a second compound semiconductor device coupled in a face-to-face arrangement. The first compound semiconductor device can be coupled to the second compound semiconductor device such that a cavity is formed that includes a first gate electrical contact of the first compound semiconductor device and a second gate electrical contact of the second compound semiconductor device. A gap can be present between the first gate electrical contact and the second gate electrical contact.

Abstract: A compound semiconductor HEMT can be constructed as a graded bi-layer of AlGaN on AlGaN to create a 2DEG channel region in the underlying AlGaN region, and can employ techniques to create both depletion mode and enhancement mode HEMT structures. Injection transistor embodiments, electric field control embodiments, and bi-directional multi-gate embodiments are shown and described as well.

Abstract: Techniques to convert a silicon layer into a silicon dioxide layer, such as by diffusing oxygen in an oxygen-rich region into the silicon layer to react with the silicon layer to form the silicon dioxide layer. As a result, the conductive silicon layer is removed and the electric field lines originating from the drain node no longer terminate in the silicon layer. Therefore, the electric field in gallium nitride (GaN) is significantly reduced, and a thinner GaN layer may be used for high-voltage devices.

Abstract: Various engineered substrate techniques for gallium nitride devices are described that address limitations of conventional substrate approaches. For example, various techniques are described for implementing silicon carbide-on-poly-aluminum nitride (poly-AlN) and sapphire-on-poly-AlN engineered substrates using smart cut processes, hydrogen implantation and exfoliation, and advanced field management approaches to improve device performance while maintaining cost-effectiveness. The engineered substrates described provide the lattice matching and thermal benefits of silicon carbide or sapphire surfaces, for example, while utilizing the CTE matching and cost advantages of poly-AlN handle wafers.

Abstract: Techniques to increase the number of current paths (or “channels”) in a GaN transistor, without increasing the device area, thereby decreasing the on-resistance. In addition, this disclosure describes techniques to utilize back-side field management to improve the device's performance. For example, the techniques can include using p-type implantation into the substrate, e.g., silicon carbide (SiC), as a field management tool to form a superjunction device, thereby increasing the effective field and reducing the on-resistance multiplied by the output charge (Qoss).

Abstract: In one or more implementations, a semiconductor device can include a first compound semiconductor device coupled to a second compound semiconductor device coupled in a face-to-face arrangement. The first compound semiconductor device can be coupled to the second compound semiconductor device such that a cavity is formed that includes a first gate electrical contact of the first compound semiconductor device and a second gate electrical contact of the second compound semiconductor device. A gap can be present between the first gate electrical contact and the second gate electrical contact.

Abstract: A heat spreader is described that may include a substrate of a top device, and that cools the top die of a flip-chipped die combination. The heat spreader includes a material with a high thermal conductivity, such as a material including diamond. The top heat spreader substrate may have a connection to the bottom base substrate, e.g., carrier.

Abstract: Using various techniques, a metal backside field plate is formed at the end of the process. In an example, the GaN layer is grown, the HEMT is fabricated, and the substrate is thinned. A via is made through the thinned substrate and GaN epi to the underside of the source electrode and the metal backside field plate is then deposited. In another example, a pocket for the backside field plate is formed completely through the thickness of the substrate, a via is formed through the GaN to the source electrode, and then the metal backside field plate is deposited in the pocket.

Abstract: Described is a GaN fabrication process using titanium nitride (TiN) and tungsten (W) metallization optimized for high-temperature operation. An aluminum-free gate stack and backend process are disclosed. Ohmic contacts may be formed by a highly doped N+ GaN layer enabling low contact resistance with titanium nitride (TiN) and tungsten (W) metals. The gate metal thickness may be increased to counteract the higher resistivity of tungsten (W) compared to aluminum (Al). The resulting process uses only high melting point materials and is compatible with silicon carbide (SiC) or sapphire substrates for robust high-temperature GaN device performance.

Abstract: Integrated circuits can include semiconductor devices with back-side field plates. The semiconductor devices can be formed on substrates that have conductive layers located within the substrates. The conductive layers can include at least one of a conducting material or a semi-conducting material that modifies an electric field produced by the semiconductor devices. The semiconductor devices can include one or more semiconductor layers that include one or more materials having a compound material that includes at least one Group 13 element and at least one Group 15 element.

Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

Abstract: An enhancement mode compound semiconductor field-effect transistor (FET) includes a source, a drain, and a gate located therebetween. The transistor further includes a first gallium nitride-based hetero-interface located under the gate and a buried region, located under the first hetero-interface, the buried p-type region configured to determine an enhancement mode FET turn-on threshold voltage to permit current flow between the source and the drain.

Abstract: Various techniques for impurity dopant reduction in GaN regrowth are described. In a first technique, a barrier layer, such as AlN, can be formed at a regrowth interface before the regrown GaN layer. The barrier layer can bury the impurities at the regrowth interface and reduce their effect on the layers above that include the channel of the device, e.g., transistor. In a second technique, a buffer layer, such as a carbon-doped GaN layer, can be formed at the regrowth interface before the regrown GaN layer. Carbon can act as an acceptor to compensate for the dopants. e.g., silicon, and cancel their electronic effect on the above layers. In a third technique, a hydrogen bake treatment can be performed before the GaN regrowth. Hydrogen can desorb a thin layer of GaN at the regrowth interface, which is the GaN layer with the highest concentration of impurities.

Abstract: Integrated circuits can include semiconductor devices with back-side field plates. The semiconductor devices can be formed on substrates that have conductive layers located within the substrates. The conductive layers can include at least one of a conducting material or a semi-conducting material that modifies an electric field produced by the semiconductor devices. The semiconductor devices can include one or more semiconductor layers that include one or more materials having a compound material that includes at least one Group 13 element and at least one Group 15 element.

Abstract: Electric field management techniques in GaN based semiconductors that utilize patterned regions of differing conductivity under the active GaN device, such as a GaN high electron mobility transistor (HEMT), are described. As an example, a patterned layer of oxidized silicon can be formed superjacent a layer of silicon dioxide during or prior to the heteroepitaxy of GaN or another semiconductor material. These techniques can be useful for back-side electric field management because a silicon layer, for example, can be made conductive to act as a back-side field plate.

Abstract: Techniques that separate the heat generation from the active device and that add a thermal heat shield layer between the heat generation and the active device to reduce the channel temperature in the areas that determine the reliability of a semiconductor device.

Abstract: A gallium nitride (GaN) semiconductor device, such as a field-effect transistor (FET), is described with a design that can enable the semiconductor device to handle high current and high voltage simultaneously. For example, the device can have highly doped n-type N+ regions to ensure low contact resistance and high current. The semiconductor device can have a lightly conducting region next to the drain side of the gate contact, and the device can have a more highly conducting region further from the edge of the drain side of the gate contact. The semiconductor device can handle high current because of the low contact resistance and highly doped drain region but can handle a high electric field because of the lightly doped region near the drain edge of the gate contact. The semiconductor device can be formed in GaN by forming the original N+/N? structure, and then etching a portion of it away, and then regrowing the barrier layer.

Abstract: Electric field management techniques in GaN based semiconductors that utilize patterned regions of differing conductivity under the active GaN device, such as a GaN high electron mobility transistor (HEMT), are described. As an example, a patterned layer of oxidized silicon can be formed superjacent a layer of silicon dioxide during or prior to the heteroepitaxy of GaN or another semiconductor material. These techniques can be useful for back-side electric field management because a silicon layer, for example, can be made conductive to act as a back-side field plate.

Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

Abstract: A semiconductor device including a transistor having a threshold voltage for switching the transistor from a first conductive state to a second conductive state. The transistor includes a first region formed by a first compound semiconductor material and a second region formed by a second compound semiconductor material, where the second region overlying the first region and forming a two-dimensional electron gas (2DEG) at a junction with the first region. The transistor further includes a buried field plate disposed proximate to the first region so that the 2DEG is interposed between the buried field plate and the second region. The semiconductor device further includes a control circuit configured to adjust the threshold voltage of the transistor by providing a bias voltage to the buried field plate responsive to an input signal received at the transistor.