Abstract: Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.

Abstract: Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.

Abstract: A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride.

Abstract: A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished.

Abstract: A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride.

Abstract: A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished.

Abstract: A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished.

Abstract: A shallow trench isolation (STI) structure and methods for forming the same provide an STI structure with a top surface formed completely of silicon nitride. The methods for forming the STI structures provide for at least one nitride deposition step followed by a further nitride deposition step to re-fill divots that occur along the upper portions of the trench sidewalls.

Abstract: Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.

Abstract: A shallow trench isolation (STI) structure and methods for forming the same provide an STI structure with a top surface formed completely of silicon nitride. The methods for forming the STI structures provide for at least one nitride deposition step followed by a further nitride deposition step to re-fill divots that occur along the upper portions of the trench sidewalls.

Abstract: A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished.

Abstract: A method, system and encoded computer instructions provide for automatic generation of a metrology recipe without referencing a wafer. The highly accurate metrology recipe provides for locating measurement locations corresponding to test features on the wafer and directing the metrology tool to the locations, by calculating coordinates for the measurement locations based on mask data, lithography tool data, CAD data and process data. The metrology recipe directs the metrology tool to within 10 microns of test features formed on the wafer. Criteria may be input to a data base to identify multiple existing recipes and the automatically generated recipe may be generated to replace each identified recipe.

Abstract: A method, system and encoded computer instructions provide for automatic generation of a metrology recipe without referencing a wafer. The highly accurate metrology recipe provides for locating measurement locations corresponding to test features on the wafer and directing the metrology tool to the locations, by calculating coordinates for the measurement locations based on mask data, lithography tool data, CAD data and process data. The metrology recipe directs the metrology tool to within 10 microns of test features formed on the wafer. Criteria may be input to a data base to identify multiple existing recipes and the automatically generated recipe may be generated to replace each identified recipe.