Patents by Inventor Daniel Platzker

Daniel Platzker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Single event upset mitigation for electronic design synthesis
    Patent number: 9275179
    Abstract: Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the synthesized design. After a circuit design has been synthesized to a particular abstraction level, a static timing analysis procedure is run on the design. The slack values for paths within the design are determined based upon the static timing analysis procedure. Subsequently, delays are added to selected paths within the design based upon the slack values.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: March 1, 2016
    Assignee: Mentor Graphics Corporation
    Inventors: Daniel Platzker, Jeffrey Alan Kaady, Ashish Kapoor
  • Single Event Upset Mitigation for Electronic Design Synthesis
    Publication number: 20140289686
    Abstract: Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the synthesized design. After a circuit design has been synthesized to a particular abstraction level, a static timing analysis procedure is run on the design. The slack values for paths within the design are determined based upon the static timing analysis procedure. Subsequently, delays are added to selected paths within the design based upon the slack values.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 25, 2014
    Applicant: Mentor Graphics Corporation
    Inventors: Daniel Platzker, Jeffrey Alan Kaady, Ashish Kapoor
  • Single event upset mitigation for electronic design synthesis
    Patent number: 8719747
    Abstract: Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the synthesized design. After a circuit design has been synthesized to a particular abstraction level, a static timing analysis procedure is run on the design. The slack values for paths within the design are determined based upon the static timing analysis procedure. Subsequently, delays are added to selected paths within the design based upon the slack values.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: May 6, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Daniel Platzker, Jeffrey Alan Kaady, Ashish Kapoor
  • Single Event Upset Mitigation for Electronic Design Synthesis
    Publication number: 20130198701
    Abstract: Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the synthesized design. After a circuit design has been synthesized to a particular abstraction level, a static timing analysis procedure is run on the design. The slack values for paths within the design are determined based upon the static timing analysis procedure. Subsequently, delays are added to selected paths within the design based upon the slack values.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Inventors: Daniel Platzker, Jeffrey Alan Kaady, Ashish Kapoor