Abstract: A detector device for calibrating a digital filter to replicate a transfer function of a signal processing apparatus, comprising: a first input to receive a first signal; a second input configured to receive a response signal of the signal processing apparatus to the first signal; a controllable FIR filter; a comparison-block to compare the phase and amplitude after a correction has been applied by the controllable FIR filter; a feedback loop; and an interpolation-block; wherein the at least one detector is configured to determine, at least, the feedback control signal at a first frequency and at a second frequency, and wherein the interpolation-block is configured to interpolate to determine calibration information for programming of the transfer function of said digital filter.

Abstract: Examples implementations relate to configuration of computational drives. An example computational drive includes a housing to be inserted in a drive bay of a host device, and persistent storage. The computational drive may also include a processor to respond to an insertion of the housing into the drive bay of the host device by configuring the computational drive to operate as a new node of a distributed file system, and connecting the computational drive to the distributed file system as the new node.

Abstract: Examples implementations relate to configuration of computational drives. An example computational drive includes a housing to be inserted in a drive bay of a host device, and persistent storage. The computational drive may also include a processor to respond to an insertion of the housing into the drive bay of the host device by configuring the computational drive to operate as a new node of a distributed file system, and connecting the computational drive to the distributed file system as the new node.

Abstract: A medical imaging demonstration image library creation method is provided. The method includes receiving data corresponding to a user acquired image of a subject obtained via operation of an X-ray imaging system and further receiving input from a user identifying the user acquired image of the subject as a desired demonstration image. The method also includes adding the user acquired image of the subject to a demonstration image library as a first demonstration image.

Abstract: A system and method for including and correcting subject orientation data in a digital radiographic image. A subject is positioned in an X-ray imaging system and an orientation of the subject is entered into the X-ray imaging system. The subject is imaged with an X-ray exposure to create an X-ray image of the subject. An operator reviews the X-ray image of the subject and subject orientation data. If the subject orientation data is not correct, the operator may correct the subject orientation data so that it matches the subject's anatomy during the X-ray exposure. The correct subject orientation data is then saved and is part of the X-ray image and Digital Imaging and Communications in Medicine (DICOM) header when sent to a Picture Archiving and Communication System (PACS).

Abstract: A series (20) of original instructions for a single processor is translated into implementing instructions for executions distributed over a plurality of processors (12,16) of different type. The series (20) of original instructions is split into successive sections (22a-c,24a,b) assigned to respective ones of the processors (12,16). Operand transfer instructions are added to the sections (22a-c,24a,b) to support data dependencies between the sections (22a-c,24a,b). The assignment includes selecting a location of a boundary in the series of original instructions between successive ones of the sections (22a-c,24a,b) so as to substantially minimize an aggregate of the execution cost factors of the original instructions as implemented and including costs for the operand transfer instructions. Preferably, the locations of the boundaries are determined from a search among different boundaries positions.

Abstract: A plurality of digital signal processors (10), each contains a signal processing core (22), a memory (20) coupled to the processing core (22) and a multiplexed data input (16) coupled to the memory (20). Each digital signal processor has a plurality of outputs for outputting data from the signal processing core (22). A remote write only structure (14a-d) couples outputs of respective groups of the digital signal processors (10) each to the multiplexed data input (16) of respective particular digital signal processor (10), the respective group for the particular digital signal processor (10) not including the particular digital signal processor (10). Thus, each processor (10) writes data for other processors directly from the processor, without storing the data in memory first for handling by an I/O processor, and reads data from other processors (10) via memory, where it is received via an input that does not share resources with the output of the processor (10).

Abstract: Aspects involve effectively separating communication hardware in a data processing system by introducing a communication device for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication device provide the communication support for the respective processor. Accordingly, in certain embodiments, a data processing system is provided with a computation, a communication support and a communication network layer.

Abstract: The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200).